144 lines
3.5 KiB
C
144 lines
3.5 KiB
C
/** @file
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Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiPei.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SiliconInitLib.h>
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#include "PeiGpioTable.h"
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/**
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Tigerlake Simics board configuration init function for PEI post memory phase.
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PEI_BOARD_CONFIG_PCD_INIT
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@param Content pointer to the buffer contain init information for board init.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_INVALID_PARAMETER The parameter is NULL.
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**/
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EFI_STATUS
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EFIAPI
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TigerLakeSimicsInit (
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VOID
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)
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{
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PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableTglSimics);
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PcdSet16S (PcdBoardGpioTableSize, sizeof (mGpioTableTglSimics) / sizeof(GPIO_INIT_CONFIG));
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PcdSet8S (PcdUsb20OverCurrentPinPort0, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort1, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort2, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort3, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort4, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort5, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort6, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort7, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort8, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort9, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort10, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort11, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort12, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort13, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort14, 0x0);
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PcdSet8S (PcdUsb20OverCurrentPinPort15, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort0, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort1, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort2, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort3, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort4, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort5, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort6, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort7, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort8, 0x0);
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PcdSet8S (PcdUsb30OverCurrentPinPort9, 0x0);
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PcdSet8S (PcdCpuUsb30PortEnable, 0x0F);
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PcdSet8S (PcdSataPortsEnable0, 0x1);
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return EFI_SUCCESS;
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}
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/**
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Configures GPIO
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@param[in] GpioTable Point to Platform Gpio table
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@param[in] GpioTableCount Number of Gpio table entries
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**/
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VOID
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ConfigureGpio (
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IN GPIO_INIT_CONFIG *GpioDefinition,
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IN UINT16 GpioTableCount
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)
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{
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
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Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
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DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
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}
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/**
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Configure GPIO
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**/
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VOID
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GpioInit (
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VOID
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)
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{
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ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) PcdGet16 (PcdBoardGpioTableSize));
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return;
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}
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/**
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Configure GPIO and SIO
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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TigerLakeSimicsBoardInitBeforeSiliconInit (
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VOID
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)
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{
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TigerLakeSimicsInit ();
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GpioInit ();
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///
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/// Do Late PCH init
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///
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LateSiliconInit ();
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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TigerLakeSimicsBoardInitAfterSiliconInit (
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VOID
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)
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{
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return EFI_SUCCESS;
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}
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