87 lines
5.1 KiB
C
87 lines
5.1 KiB
C
//
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// Automatically generated by GenNvs ver 2.4.6
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// Please DO NOT modify !!!
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//
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/**@file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2017 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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//
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// Define DTBT NVS Area operation region.
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//
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#ifndef _D_TBT_NVS_AREA_DEF_H_
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#define _D_TBT_NVS_AREA_DEF_H_
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#pragma pack (push,1)
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typedef struct {
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UINT8 TbtWin10Support; ///< Offset 0 TbtWin10Support
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UINT8 ThunderboltHotNotify; ///< Offset 1 Notify on Hot Plug for TBT devices
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UINT8 TbtAcpiRemovalSupport; ///< Offset 2 TbtAcpiRemovalSupport
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UINT8 TbtWakeupSupport; ///< Offset 3 Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
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UINT8 DiscreteTbtSupport; ///< Offset 4 Thunderbolt (TM) support
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UINT8 TbtGpioFilter; ///< Offset 5 Gpio filter to detect USB Hotplug event
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UINT32 TbtCioPlugEventGpioNo0; ///< Offset 6 TbtCioPlugEventGpioNo
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UINT32 TbtPcieRstGpioNo0; ///< Offset 10 TbtPcieRstGpioNo
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UINT8 TbtPcieRstGpioLevel0; ///< Offset 14 TbtPcieRstGpioLevel
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UINT8 CurrentDiscreteTbtRootPort; ///< Offset 15 Current Port that has plug event
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UINT8 RootportSelected0; ///< Offset 16 Root port Selected by the User
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UINT8 RootportSelected0Type; ///< Offset 17 Root port Type
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UINT8 RootportSelected1; ///< Offset 18 Root port Selected by the User
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UINT8 RootportSelected1Type; ///< Offset 19 Root port Type
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UINT8 RootportEnabled0; ///< Offset 20 Root port Enabled by the User
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UINT8 RootportEnabled1; ///< Offset 21 Root port Enabled by the User
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UINT32 TbtCioPlugEventGpioNo1; ///< Offset 22 TbtCioPlugEventGpioNo
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UINT32 TbtPcieRstGpioNo1; ///< Offset 26 TbtPcieRstGpioNo
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UINT8 TbtPcieRstGpioLevel1; ///< Offset 30 TbtPcieRstGpioLevel
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UINT8 TBtCommonGpioSupport; ///< Offset 31 Set if Single GPIO is used for Multi/Different Controller Hot plug support
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UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 32 Root Port type for which SCI Triggered
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UINT8 DTbtControllerEn0; ///< Offset 33 DTbtController0 is enabled or not. @deprecated since revision 2
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UINT8 DTbtControllerEn1; ///< Offset 34 DTbtController1 is enabled or not. @deprecated since revision 2
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UINT8 DTbtRtd3; ///< Offset 35 DTBT Rtd3.
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UINT16 DTbtRtd3OffDelay; ///< Offset 36 DTBT RTD3 Off delay in ms.
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UINT8 DTbtRtd3ClkReq; ///< Offset 38 Enable DTBT RTD3 CLKREQ mask.
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UINT16 DTbtRtd3ClkReqDelay; ///< Offset 39 DTBT RTD3 CLKREQ mask delay.
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UINT8 DTbtGo2SxCommand; ///< Offset 41 DTBT Go2Sx command.
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//
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// Revision Field:
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//
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UINT8 DTbtRevision; ///< Offset 42 Revison of DTbtNvsArea
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UINT8 TbtBootDeviceConnected; ///< Offset 43 Tbt Boot Device Connected.
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UINT8 DTbtControllerPresentNo; ///< Offset 44 Total DTBT controllers present.
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UINT8 DTbtRtd3OffDelayOptEn; ///< Offset 45 DTBT RTD3 Off delay Optimization Enable.
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} DTBT_NVS_AREA;
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#pragma pack(pop)
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#endif
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