274 lines
9.1 KiB
C
274 lines
9.1 KiB
C
/** @file
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Header file for the generic USB4 Router implementation
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _USB4_ROUTER_DEFS_H_
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#define _USB4_ROUTER_DEFS_H_
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#include <Uefi.h>
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#include <Usb4Common.h>
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#include <Usb4ConfigSpace.h>
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#include <Usb4ConfigLayer.h>
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#include <Usb4CsIo.h>
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#define RT_NOTIFICATION_TIMEOUT_IN_MS 0xFE
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#define USB_VENDOR_ID_INTEL_1 0x8086
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#define USB_VENDOR_ID_INTEL_2 0x8087
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typedef struct _USB4_ROUTER USB4_ROUTER, *PUSB4_ROUTER;
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//
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// Lane adapter status indicator
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//
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typedef struct {
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// Indicate Lane0 adapter
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UINT32 Lane0 : 1;
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// Indicate lane bonding enabled
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UINT32 LbEnabled : 1;
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UINT32 Reserved : 30;
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} LANE_ADAPTER_STATUS, *PLANE_ADAPTER_STATUS;
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//
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// Lane adapter capability support fields
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//
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typedef struct {
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UINT32 SupportedLinkSpeeds : 4;
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UINT32 SupportedLinkWidths : 6;
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UINT32 Cl0sSupport : 1;
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UINT32 Cl1Support : 1;
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UINT32 Cl2Support : 1;
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UINT32 Reserved : 19;
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} LANE_ADAPTER_CAP, *PLANE_ADAPTER_CAP;
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//
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// Lane adapter specific variables for lane adapter implementation
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//
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typedef struct _USB4_ADAPTER_LANE {
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LANE_ADAPTER_STATUS Status;
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LANE_ADAPTER_CAP AdpCap;
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// Downstream Router instance connecting this port
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PUSB4_ROUTER DsRouter;
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// Port group capability offset
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UINT8 PgCapReg;
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// Paired USB3 adapter number in router
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UINT8 PairedUsbAdp;
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// Paired PCIe adapter number in router
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UINT8 PairedPcieAdp;
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// Bit mask for used Egress HopId 10 (bit 0) ~ 41 (bit 31)
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UINT32 HopIdMask;
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// Ingress HopId assigned for DP tunneling main path
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UINT16 IngressDpMainHopId[USB4_DP_STREAM_MAX];
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// Ingress HopId assigned for DP tunneling aux path
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UINT16 IngressDpAuxHopId[USB4_DP_STREAM_MAX];
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// Egress HopId assigned for DP tunneling main path
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UINT16 EgressDpMainHopId[USB4_DP_STREAM_MAX];
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// Egress HopId assigned for DP tunneling aux path
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UINT16 EgressDpAuxHopId[USB4_DP_STREAM_MAX];
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} USB4_ADAPTER_LANE, *PUSB4_ADAPTER_LANE;
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//
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// USB3 adapter status indicator
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//
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typedef struct {
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// Indicate USB3 path is enabled in this USB3 adapter
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UINT32 PathEnable : 1;
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UINT32 Reserved : 31;
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} USB3_ADAPTER_STATUS, *PUSB3_ADAPTER_STATUS;
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//
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// USB3 adapter specific variables for USB3 adapter implementation
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//
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typedef struct _USB4_ADAPTER_USB3 {
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USB3_ADAPTER_STATUS Status;
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// Paired lane adapter in router
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UINT8 PairedLaneAdp;
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} USB4_ADAPTER_USB3, *PUSB4_ADAPTER_USB3;
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//
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// PCIe adapter status indicator
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//
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typedef struct {
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// Indicate PCIe path is enable in this PCIe adapter
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UINT32 PathEnable : 1;
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UINT32 Reserved : 31;
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} PCIE_ADAPTER_STAUS, *PCIE_ADAPTER_STATUS;
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//
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// PCIe adapter specific variables for PCIe adapter implementation
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//
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typedef struct _USB4_ADAPTER_PCIE {
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PCIE_ADAPTER_STAUS Status;
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UINT8 PairedLaneAdp;
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} USB4_ADAPTER_PCIE, *PUSB4_ADAPTER_PCIE;
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//
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// Adapter type specific structure
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//
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typedef union _USB4_ADAPTER_SPECIFIC {
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USB4_ADAPTER_LANE Lane;
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USB4_ADAPTER_USB3 AdpUsb3;
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USB4_ADAPTER_PCIE AdpPcie;
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} USB4_ADAPTER_SPECIFIC, *PUSB4_ADAPTER_SPECIFIC;
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//
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// USB4 adapter structure
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//
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typedef struct _USB4_ADAPTER {
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// Adapter type defined in USB4 spec
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USB4_ADAPTER_TYPE Type;
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// Router instance containing this adapter
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PUSB4_ROUTER Router;
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// Max input HopId supported defined in adapter config space
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UINT16 MaxInputHopId;
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// Max output HopId supported defined in adapter config space
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UINT16 MaxOutputHopId;
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// Adapter number of this adapter
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UINT8 AdpNum;
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// Next capability offset defined in adapter config space
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UINT8 NextCap;
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// Lane/DP/PCIe/USB3 capability offset in adapter config space
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UINT8 AdpCapReg;
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// TMU capability offset in adapter config space
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UINT8 TmuCapReg;
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// VSC0 capability offset in adapter config space (Used by TBT3 implementation)
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UINT16 Vsc0Reg;
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// VSC1 capability offset in adapter config space (Used by TBT3 implementation)
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UINT16 Vsc1Reg;
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// Adapter type dependent structure
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USB4_ADAPTER_SPECIFIC AdpDep;
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} USB4_ADAPTER, *PUSB4_ADAPTER;
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//
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// USB4 router state indicator
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//
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typedef struct _ROUTER_STATE {
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// Router is in use
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UINT32 InUse : 1;
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// Router is a TBT3 Router
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UINT32 Tbt3 : 1;
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// Internal USB3 Host controller is implemented
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UINT32 Usb3HcImpl : 1;
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// Internal USB3 Host controller is enabled
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UINT32 Usb3HcOn : 1;
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// PCIe Tunneling is enabled
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UINT32 PtOn : 1;
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// USB3 Tunneling is enabled
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UINT32 UtOn : 1;
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// USB3 adapter is present
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UINT32 Usb3 : 1;
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// PCIe adapter is present
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UINT32 Pcie : 1;
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// DP-IN adapter is present
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UINT32 DpIn : 1;
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// DP-OUT adapter is present
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UINT32 DpOut : 1;
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} ROUTER_STATE, *PROUTER_STATE;
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//
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// <TBT3>
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// TBT3 router VSEC_6 information
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//
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typedef struct _TBT3_VSEC_6 {
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UINT8 Usb4Ports;
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UINT8 CommonRegionLen;
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UINT16 PortRegionLen;
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} TBT3_VSEC_6, *PTBT3_VSEC_6;
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//
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// Router Types of router instance.
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//
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typedef enum _USB4_ROUTER_TYPE {
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USB4_ROUTER_HOST_ROUTER = 1,
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USB4_ROUTER_ALPINE_RIDGE,
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USB4_ROUTER_TITAN_RIDGE,
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USB4_ROUTER_YOSEMITE_FALLS,
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USB4_ROUTER_MAPLE_RIDGE,
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USB4_ROUTER_TGL_ITBT,
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USB4_ROUTER_USB4,
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USB4_ROUTER_INVALID
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} USB4_ROUTER_TYPE, *PUSB4_ROUTER_TYPE;
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#define GET_ROUTER(Addr, Field) ((PUSB4_ROUTER)((UINT8 *)Addr - (UINTN)(&((PUSB4_ROUTER)0)->Field)))
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//
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// USB4 router entity in domain
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//
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struct _USB4_ROUTER {
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// Router topology ID in domain (Defined in USB4 configuration layer)
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TOPOLOGY_ID TopologyId;
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// Router depth in domain topology
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UINT8 Depth;
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UINT16 VendorId;
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UINT16 DeviceId;
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USB4_ROUTER_TYPE RouterType;
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// Domain context of this router (Used for host interface access)
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USB4_DOMAIN_CONTEXT DomainContext;
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// Router state
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ROUTER_STATE State;
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UINT32 Revision;
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UINT32 NotifyTimeout;
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UINT32 Usb4Version;
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// Max Port number supported by this Router
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UINT8 MaxAdapter;
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// Router Adapter instances
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USB4_ADAPTER Adapter[USB4_ADAPTER_SUPPORT_MAX];
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// Lane Upstream Adapter number
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UINT8 LaneUpAdpNum;
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// PCIe Upstream Adapter number
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UINT8 PcieUpAdpNum;
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// USB3 Upstream Adapter number
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UINT8 Usb3UpAdpNum;
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// Host Interface Adapter number
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UINT8 HiAdpNum;
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// Router TMU capability offset in Router CS
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UINT16 TmuCapReg;
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// <TBT3> VSC1 offset for TBT3 support
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UINT16 Vsc1Reg;
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// <TBT3> VSEC6 offset for TBT3 support
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UINT16 Vsec6Reg;
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// <TBT3> VSEC6 structure used for TBT3 support
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TBT3_VSEC_6 Tbt3Vsec6;
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// Upstream router's lane adapter instance that this Router is connecting to
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PUSB4_ADAPTER UpperRtLane;
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// Upstream router instance
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PUSB4_ROUTER ParentRt;
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// Upstream router's downstream lane adapter number that this router is connecting to
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UINT8 ParentAdpNum;
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// Link list entry used in domain topology management
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LIST_ENTRY DomainEntry;
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// Downstream router count
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UINT32 DsRouterCount;
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};
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#endif
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