115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
/** @file
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Default platform setup configuration settings.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2009 - 2017 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _SETUP_CONFIGURATION_H_
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#define _SETUP_CONFIGURATION_H_
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#define SERIAL_SETUP_OPTION 1
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#define TOTAL_SIO_SERIAL_PORTS 0x4
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#define TOTAL_PCI_SERIAL_PORTS 0x1
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#define TOTAL_SERIAL_PORTS 0x5
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#define MAX_SIO_SERIAL_PORTS 0x4
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#define MAX_PCI_SERIAL_PORTS 0x4
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#define DEFAULT_CONSOLE_REDIRECTION_ENABLE 1
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#define DEFAULT_ACPI_SPCR_COM_PORT 0x0
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#define DEFAULT_TERMINAL_TYPE 0x3
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#define DEFAULT_RESOLUTION_TYPE 0x0
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#define DEFAULT_ACPI_SPCR_CONSOLE_REDIRECTION_ENABLE 1
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#define DEFAULT_ACPI_SPCR_TABLE_TERMINAL_TYPE 0x2
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#define HARDWARE_FLOW_CONTROL_SETUP_OPTION 0x1
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#define SOFTWARE_FLOW_CONTROL_SETUP_OPTION 0x2
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#define TIMEOUT_FOR_DETERMINING_LONE_ESC_CHAR 0xf4240
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#define DEFAULT_BOOT_TIMEOUT 0x1
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#define DEFAULT_FAST_BOOT 0
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#define DEFAULT_QUIET_BOOT 0
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#define FORCE_USER_TO_SETUP_ON_FIRST_BOOT 0
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#define SHOW_ADVANCED_FORMSET 1
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#define FORCE_USER_TO_SETUP_IF_BOOT_WITH_DEFAULT 0
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#define LOAD_DEFAULTS_IF_SECONDARY_NVRAM_INIT 1
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#define UART_SERIAL_PORT_0_INDEX 0x0
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#define UART_SERIAL_PORT_1_INDEX 0x1
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#define UART_SERIAL_PORT_2_INDEX 0x2
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#define UART_SERIAL_PORT_3_INDEX 0x3
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#define PCI_SERIAL_PORT_0_INDEX 0x4
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#define PCI_SERIAL_PORT_1_INDEX 0x5
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#define PCI_SERIAL_PORT_2_INDEX 0x6
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#define PCI_SERIAL_PORT_3_INDEX 0x7
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#define OFFSET_0 0x0
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#define OFFSET_1 0x1
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#define OFFSET_2 0x2
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#define OFFSET_3 0x3
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#define OFFSET_4 0x4
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#define OFFSET_5 0x5
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#define OFFSET_6 0x6
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#define OFFSET_7 0x7
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#define OFFSET_8 0x8
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#define OFFSET_9 0x9
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#define OFFSET_10 0xa
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#define OFFSET_11 0xb
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#define OFFSET_12 0xc
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#define OFFSET_13 0xd
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#define OFFSET_14 0xe
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#define OFFSET_15 0xf
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#define OFFSET_16 0x10
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#define OFFSET_17 0x11
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#define OFFSET_18 0x12
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#define OFFSET_19 0x13
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#define OFFSET_20 0x14
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#define OFFSET_21 0x15
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#define OFFSET_22 0x16
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#define OFFSET_23 0x17
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#define OFFSET_24 0x18
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#define OFFSET_25 0x19
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#define OFFSET_26 0x1a
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#define OFFSET_27 0x1b
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#define OFFSET_28 0x1c
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#define OFFSET_29 0x1d
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#define OFFSET_30 0x1e
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#define OFFSET_31 0x1f
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#define OFFSET_32 0x20
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#define OFFSET_33 0x21
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#define OFFSET_34 0x22
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#define OFFSET_35 0x23
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#define OFFSET_36 0x24
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#define OFFSET_37 0x25
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#define OFFSET_38 0x26
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#define OFFSET_39 0x27
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#define ENGLISH en-US
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#endif
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