70 lines
2.5 KiB
C
70 lines
2.5 KiB
C
/** @file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2012 - 2018 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _DXE_SA_POLICY_UPDATE_H_
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#define _DXE_SA_POLICY_UPDATE_H_
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#include <PiDxe.h>
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#include <CpuRegs.h>
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#include <SetupVariable.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Protocol/SaPolicy.h>
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#include <Library/CpuPlatformLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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//
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// Haddock Creek
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//
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#define DIMM_SMB_SPD_P0C0D0_HC 0xA2
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#define DIMM_SMB_SPD_P0C0D1_HC 0xA0
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#define DIMM_SMB_SPD_P0C1D0_HC 0xA6
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#define DIMM_SMB_SPD_P0C1D1_HC 0xA4
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#define DIMM_SMB_SPD_P0C0D2_HC 0xAA
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#define DIMM_SMB_SPD_P0C1D2_HC 0xA8
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//
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// Sawtooth Peak
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// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
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//
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#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
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#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
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#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
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#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
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#endif
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