63 lines
2.5 KiB
C
63 lines
2.5 KiB
C
/** @file
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Resources initialization values for Thunderbolt(TM).
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification
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**/
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#ifndef _DISCRETE_TBT_RESOURCES_INIT_VALUES_H_
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#define _DISCRETE_TBT_RESOURCES_INIT_VALUES_H_
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//
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//As per the Bios implementation Guide
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//(Table 2.3: Host Router resource allocation/reservation scheme) ,
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//we need to allocate enough resources based on Host router type
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//one port or two port
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//
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//
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// One port dTBT default init values
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//
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#define DTBT_PCIE_EXTRA_BUS_RSVD_ONE_PORT_DEFAULT 56
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#define DTBT_PCIE_MEM_RSVD_ONE_PORT_DEFAULT 356
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#define DTBT_PCIE_MEM_ADDRRNGMAX_ONE_PORT_DEFAULT 26
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#define DTBT_PCIE_PMEM_RSVD_ONE_PORT_DEFAULT 544
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#define DTBT_PCIE_PMEM_ADDRRNGMAX_ONE_PORT_DEFAULT 28
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//
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// Two ports dTBT default init values
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//
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#define DTBT_PCIE_EXTRA_BUS_RSVD_TWO_PORT_DEFAULT 106
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#define DTBT_PCIE_MEM_RSVD_TWO_PORT_DEFAULT 737
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#define DTBT_PCIE_MEM_ADDRRNGMAX_TWO_PORT_DEFAULT 26
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#define DTBT_PCIE_PMEM_RSVD_TWO_PORT_DEFAULT 1184
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#define DTBT_PCIE_PMEM_ADDRRNGMAX_TWO_PORT_DEFAULT 28
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#endif
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