127 lines
4.1 KiB
Plaintext
127 lines
4.1 KiB
Plaintext
/** @file
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Intel Processor Power Management ACPI Code.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "CpuPowerMgmt.h"
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DefinitionBlock (
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"CPU0PSD.aml",
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"SSDT",
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0x02,
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"PmRef",
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"Cpu0Psd",
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0x3000
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)
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{
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External(\PF00, IntObj)
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External(\TCNT, FieldUnitObj)
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External(\_SB.CFGD, FieldUnitObj)
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External(\_SB.PR00, DeviceObj)
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External (HTRO)
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External (CORE)
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External (MDID)
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External (SCM0)
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External (SCM1)
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External (BCNT)
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External (CM00)
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Scope(\_SB.PR00)
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{
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//
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// Get _PSD
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// Arg0 = CPU Index
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// Arg1 = Core and Module Information
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// BITS 7:4 has the Num of processors in that module
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// BITS 3:0 denotes the ModuleID of that core
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//
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Method(GPSD, 2)
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{
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Name(HPSD,Package() // HW_ALL
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{
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Package() { 5, // NumEntries. Current Value is 5.
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0, // Revision. Current Value is 0.
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0, // Domain.
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0xFE, // Coordination type 0xFE = HW_ALL
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0x80 // Number of processors.
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}
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})
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Name(SPSD,Package() // SW_ALL
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{
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Package() { 5, // NumEntries. Current Value is 5.
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0, // Revision. Current Value is 0.
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0, // Domain.
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0xFC, // Coordination type 0xFC = SW_ALL
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0x80 // Number of processors.
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}
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})
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If (LAnd(And(\_SB.CFGD, PPM_TURBO_BOOST_MAX), And(\_SB.CFGD, PPM_HWP)))
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{
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Store (Arg0, Index(DerefOf(Index(HPSD, 0)),2)) // Domain
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Store (1, Index(DerefOf(Index(HPSD, 0)),4)) // Number of processors belonging to the domain.
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} Else {
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//
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// For Hetero Cores, Each module have to be in its seperate domain
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//
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If (HTRO) {
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//
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// Number of processors belonging to the domain.
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//
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Store (ShiftRight (AND (Arg1, 0xF0),4), Index (DerefOf (Index (HPSD, 0)), 4))
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Store (ShiftRight (AND (Arg1, 0xF0),4), Index (DerefOf (Index (SPSD, 0)), 4))
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Store (AND (Arg1, 0x0F), Index (DerefOf (Index (HPSD, 0)), 2)) // Domain
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Store (AND (Arg1, 0x0F), Index (DerefOf (Index (SPSD, 0)), 2)) // Domain
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} Else {
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Store (TCNT, Index (DerefOf (Index (HPSD, 0)), 4))
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Store (TCNT, Index (DerefOf (Index (SPSD, 0)), 4))
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}
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}
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If(And(PF00,0x0800))
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{
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Return(HPSD)
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}
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Return(SPSD)
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}
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Method(_PSD,0)
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{
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Return(GPSD(0, CM00))
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}
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}
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} // End of Definition Block
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