123 lines
4.2 KiB
C
123 lines
4.2 KiB
C
/** @file
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CPU Config Block.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_CONFIG_H_
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#define _CPU_CONFIG_H_
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#define CPU_CONFIG_REVISION 5
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extern EFI_GUID gCpuConfigGuid;
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#pragma pack (push,1)
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/**
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CPU Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Add SmbiosType4MaxSpeedOverride.
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<b>Revision 3</b>:
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- Add AvxDisable & Avx3Disable.
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<b>Revision 4</b>:
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- Add X2ApicSupport.
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<b>Revision 5</b>:
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- Deprecate Avx3Disable
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 MicrocodePatchRegionSize;
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EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor.
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/**
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Enable or Disable Advanced Encryption Standard (AES) feature.
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For some countries, this should be disabled for legal reasons.
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- 0: Disable
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- <b>1: Enable</b>
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**/
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UINT32 AesEnable : 1;
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/**
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Enable or Disable Trusted Execution Technology (TXT) feature.
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- 0: Disable
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- <b>1: Enable</b>
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**/
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UINT32 TxtEnable : 1;
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UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
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/**
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Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number.
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- <b>0: Disable</b>
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- 1: Enable
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- 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM is set, it is disabled.
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**/
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UINT32 PpinSupport : 2;
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/**
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Enable or Disable #AC machine check on split lock.
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- <b>0: Disable</b>
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- 1: Enable
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**/
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UINT32 AcSplitLock : 1;
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/**
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Enable or Disable Avx.
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- 1: Disable
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- <b> 0: Enable</b>
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**/
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UINT32 AvxDisable : 1;
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/**
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@deprecated
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Enable or Disable Avx3.
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- <b> 1: Disable</b>
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- 0: Enable
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**/
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UINT32 Avx3Disable : 1;
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/**
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Enable or Disable X2APIC Support.
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- <b>0: Disable</b>
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- 1: Enable
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**/
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UINT32 X2ApicSupport : 1;
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UINT32 RsvdBits : 23; ///< Reserved for future use
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/**
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Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
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Value 4000 means 4000MHz.
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If this value is not zero, it dominates the field.
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If this value is zero, CPU RC will update the field according to the max radio.
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<b>default is 0.</b>
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**/
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UINT16 SmbiosType4MaxSpeedOverride;
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UINT8 Reserved0[2]; ///< Reserved for future use
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} CPU_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_CONFIG_H_
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