252 lines
10 KiB
C
252 lines
10 KiB
C
/** @file
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This file contains define definitions specific to processor
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _POWER_MGMT_DEFINITIONS_H_
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#define _POWER_MGMT_DEFINITIONS_H_
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#define CSTATE_SUPPORTED 0x1
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#define ENHANCED_CSTATE_SUPPORTED 0x2
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#define C6_C7_SHORT_LATENCY_SUPPORTED 0x01
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#define C6_C7_LONG_LATENCY_SUPPORTED 0x02
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#define C7s_SHORT_LATENCY_SUPPORTED 0x03
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#define C7s_LONG_LATENCY_SUPPORTED 0x04
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//
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// Voltage offset definitions
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//
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#define OC_LIB_OFFSET_ADAPTIVE 0
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#define OC_LIB_OFFSET_OVERRIDE 1
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//
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// Platform Power Management Flags Bit Definitions:
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// These defines are also used in CPU0CST.ASL to check platform configuration
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// and build C-state table accordingly.
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//
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#ifdef __GNUC__
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//
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// @todo Add workaround for GCC build, In GCC build the BIT can not be changed to value by GCC (ex: BIT0 can not be changed to 0x1)
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//
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#define PPM_EIST 0x1 ///< BIT 0 : Enhanced Intel Speed Step Technology.
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#define PPM_C1 0x2 ///< BIT 1 : C1 enabled, supported.
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#define PPM_C1E 0x4 ///< BIT 2 : C1E enabled.
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#define PPM_C6 0x10 ///< BIT 4 : C6 enabled, supported.
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#define PPM_C7 0x20 ///< BIT 5 : C7 enabled, supported.
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#define PPM_C7S 0x40 ///< BIT 6 : C7S enabled, supported
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#define PPM_TM 0x80 ///< BIT 7 : Adaptive Thermal Monitor.
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#define PPM_TURBO 0x100 ///< BIT 8 : Long duration turbo mode
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#define PPM_CMP 0x200 ///< BIT 9 : CMP.
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#define PPM_TSTATES 0x400 ///< BIT 10: CPU throttling states
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#define PPM_MWAIT_EXT 0x800 ///< BIT 11: MONITIOR/MWAIT Extensions supported.
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#define PPM_EEPST 0x1000 ///< BIT 12: Energy efficient P-State Feature enabled
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#define PPM_TSTATE_FINE_GRAINED 0x2000 ///< BIT 13: Fine grained CPU Throttling states
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#define PPM_CD 0x4000 ///< BIT 14: Deep Cstate - C8/C9/C10
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#define PPM_TIMED_MWAIT 0x8000 ///< BIT 15: Timed Mwait support
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#define C6_LONG_LATENCY_ENABLE 0x10000 ///< BIT 16: 1=C6 Long and Short,0=C6 Short only
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#define C7_LONG_LATENCY_ENABLE 0x20000 ///< BIT 17: 1=C7 Long and Short,0=C7 Short only
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#define C7s_LONG_LATENCY_ENABLE 0x40000 ///< BIT 18: 1=C7s Long and Short,0=C7s Short only
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#define PPM_C8 0x80000 ///< Bit 19: 1= C8 enabled/supported
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#define PPM_C9 0x100000 ///< Bit 20: 1= C9 enabled/supported
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#define PPM_C10 0x200000 ///< Bit 21: 1= C10 enabled/supported
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#define PPM_HWP 0x400000 ///< Bit 22: 1= HWP enabled/supported
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#define PPM_OC_UNLOCKED 0x1000000 ///< Bit 24: 1= Overclocking fully uncloked
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#define PPM_TURBO_BOOST_MAX 0x2000000 ///< Bit 25: 1= Intel Turbo Boost Max Technology 3.0.
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#else
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#define PPM_EIST BIT0 ///< Enhanced Intel Speed Step Technology.
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#define PPM_C1 BIT1 ///< C1 enabled, supported.
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#define PPM_C1E BIT2 ///< C1E enabled.
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#define PPM_C6 BIT4 ///< C6 enabled, supported.
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#define PPM_C7 BIT5 ///< C7 enabled, supported.
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#define PPM_C7S BIT6 ///< C7S enabled, supported
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#define PPM_TM BIT7 ///< Adaptive Thermal Monitor.
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#define PPM_TURBO BIT8 ///< Long duration turbo mode
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#define PPM_CMP BIT9 ///< CMP.
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#define PPM_TSTATES BIT10 ///< CPU throttling states
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#define PPM_MWAIT_EXT BIT11 ///< MONITIOR/MWAIT Extensions supported.
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#define PPM_EEPST BIT12 ///< Energy efficient P-State Feature enabled
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#define PPM_TSTATE_FINE_GRAINED BIT13 ///< Fine grained CPU Throttling states
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#define PPM_CD BIT14 ///< Deep Cstate - C8/C9/C10
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#define PPM_TIMED_MWAIT BIT15 ///< Timed Mwait support
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#define C6_LONG_LATENCY_ENABLE BIT16 ///< 1=C6 Long and Short,0=C6 Short only
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#define C7_LONG_LATENCY_ENABLE BIT17 ///< 1=C7 Long and Short,0=C7 Short only
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#define C7s_LONG_LATENCY_ENABLE BIT18 ///< 1=C7s Long and Short,0=C7s Short only
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#define PPM_C8 BIT19 ///< 1= C8 enabled/supported
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#define PPM_C9 BIT20 ///< 1= C9 enabled/supported
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#define PPM_C10 BIT21 ///< 1= C10 enabled/supported
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#define PPM_HWP BIT22 ///< 1= HWP enabled/supported
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#define PPM_OC_UNLOCKED BIT24 ///< 1= Overclocking fully unlocked
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#define PPM_TURBO_BOOST_MAX BIT25 ///< 1= Intel Turbo Boost Max Technology 3.0
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#endif
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#define PPM_C_STATES 0x72 ///< PPM_C1 + PPM_C6 + PPM_C7 + PPM_C7S
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//
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// The following definitions are based on assumed location for the ACPI
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// Base Address. Modify as necessary base on platform-specific requirements.
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//
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#define PCH_ACPI_PBLK 0x1810
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#define PCH_ACPI_LV2 0x1814
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#define PCH_ACPI_LV3 0x1815
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#define PCH_ACPI_LV4 0x1816
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#define PCH_ACPI_LV6 0x1818
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#define PCH_ACPI_LV5 0x1817
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#define PCH_ACPI_LV7 0x1819
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//
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// C-State Latency (us):
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// Though _CST object is core level, it is recommended that System BIOS report the
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// Package level C state latencies, so that Operating System can account for worst case
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// latency before using a specific C state. Unlike legacy platforms,
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// BIOS is no longer required to program the C_STATE_LATENCYCONTROL_n MSRs (0x60B, 0x60C, 0x633, 0x634, 0x635).
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//
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#define C1_LATENCY 1
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#define C6_LATENCY 127
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#define C7_LATENCY 253
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#define C8_LATENCY 260
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#define C9_LATENCY 487
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#define C10_LATENCY 1048
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//
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// C-State Power (mW)
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//
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#define C1_POWER 0x3E8
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#define C3_POWER 0x1F4
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#define C6_POWER 0x15E
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#define C7_POWER 0xC8
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#define C8_POWER 0xC8
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#define C9_POWER 0xC8
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#define C10_POWER 0xC8
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#define MAX_POWER_LIMIT_1_TIME_IN_SECONDS 32767
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#ifndef AUTO
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#define AUTO 0
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#endif
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#define END_OF_TABLE 0xFF
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#define CONFIG_TDP_DOWN 1
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#define CONFIG_TDP_UP 2
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#define CONFIG_TDP_DEACTIVATE 0xFF
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//
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// MMIO definitions
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//
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#define MMIO_DDR_RAPL_LIMIT 0x58E0
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#define MMIO_TURBO_POWER_LIMIT 0x59A0
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#define MMIO_TURBO_POWER_LIMIT_HIGH 0x59A4
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#define MAX_OVERCLOCKING_BINS 0x7
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///
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/// For Mobile and Halo, default PL1 time window value is 28 seconds.
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///
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#define MB_POWER_LIMIT1_TIME_DEFAULT 28
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///
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/// For Desktop, default PL1 time window value is 28 second
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///
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#define DT_POWER_LIMIT1_TIME_DEFAULT 28
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#define POWER_LIMIT1_TIME_56_SEC 56
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#define PROCESSOR_FLAVOR_MOBILE 0x04
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#define PROCESSOR_FLAVOR_DESKTOP 0x00
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#define PROCESSOR_FLAVOR_MASK (BIT3 | BIT2)
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//
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// Power definitions (Based on EMTS V1.0 for standard voltage 2.4-2.6 GHz dual-core parts.)
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//
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#define FVID_MAX_POWER 35000
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#define FVID_TURBO_POWER 35000
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#define FVID_SUPERLFM_POWER 12000
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//
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// Power definitions for LFM and Turbo mode TBD.
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//
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#define FVID_MIN_POWER 15000
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///
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/// Limit the number of P-states for different generation OS.
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///
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#define TPSS_FVID_MAX_STATES 40
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#define LPSS_FVID_MAX_STATES 16
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#define READ_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000015
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#define WRITE_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000016
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#define SVID_GET_REGISTER 0x80001018
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#define SVID_SET_REGISTER 0x80001118
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#define SVID_SET_EXCLUSIVE 0x80001218
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#define SVID_READ_REG_WHITELIST 0x80001518
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#define SVID_WRITE_REG_WHITELIST 0x80001618
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#define SVID_REGISTER_VR_ID_OFFSET 16
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#define SVID_REGISTER_VR_ID_VIRTUAL_0 4
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#define SVID_REGISTER_VR_ID_VIRTUAL_1 5
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#define SVID_REGISTER_ADDR_OFFSET 20
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#define SVID_WHITELIST_DWORD_OFFSET 20
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#define SVID_EXCLUSIVE_DISABLE 0
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#define SVID_EXCLUSIVE_ENABLE 1
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#define CPU_TDP_5_WATTS 500
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#define CPU_TDP_6_WATTS 600
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#define CPU_TDP_7_WATTS 700
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#define CPU_TDP_9_WATTS 900
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#define CPU_TDP_15_WATTS 1500
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#define CPU_TDP_10_WATTS 1000
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#define CPU_TDP_11_WATTS 1100
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#define CPU_TDP_12_WATTS 1200
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#define CPU_TDP_13_WATTS 1300
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#define CPU_TDP_25_WATTS 2500
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#define CPU_TDP_28_WATTS 2800
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#define CPU_TDP_35_WATTS 3500
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#define CPU_TDP_45_WATTS 4500
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#define CPU_TDP_46_WATTS 4600
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#define CPU_TDP_55_WATTS 5500
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#define CPU_TDP_58_WATTS 5800
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#define CPU_TDP_60_WATTS 6000
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#define CPU_TDP_63_WATTS 6300
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#define CPU_TDP_65_WATTS 6500
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#define CPU_TDP_80_WATTS 8000
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#define CPU_TDP_91_WATTS 9100
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#define CPU_TDP_95_WATTS 9500
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#define CPU_TDP_120_WATTS 12000
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#define CPU_TDP_125_WATTS 12500
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#define CPU_TDP_150_WATTS 15000
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///
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/// HDC Definitions
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///
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#define N_HDC_SUPPORT 0
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#define B_HDC_SUPPORT BIT0
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#endif
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