296 lines
13 KiB
C
296 lines
13 KiB
C
/** @file
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Register names for CPU registers
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<b>Conventions</b>
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- Definitions beginning with "MSR_" are MSRs
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- Definitions beginning with "R_" are registers
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- Definitions beginning with "B_" are bits within registers
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- Definitions beginning with "V_" are meaningful values of bits within the registers
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- Definitions beginning with "S_" are register sizes
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- Definitions beginning with "N_" are the bit position
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2004 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_REGS_H_
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#define _CPU_REGS_H_
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/**
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Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies
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Maximum Ratio Limit for each Core Group. Max ratio for groups with more
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cores must decrease monotonically. For groups with less than 4 cores, the
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max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must
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be 22 or less. For groups with more than 5 cores, the max ratio must be 16
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or less..
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@param ECX MSR_TURBO_RATIO_LIMIT (0x000001AD)
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@param EAX Lower 32-bits of MSR value.
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Described by the type MSR_TURBO_RATIO_LIMIT_REGISTER.
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@param EDX Upper 32-bits of MSR value.
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Described by the type MSR_TURBO_RATIO_LIMIT_REGISTER.
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<b>Example usage</b>
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@code
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MSR_TURBO_RATIO_LIMIT_REGISTER Msr;
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Msr.Uint64 = AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT);
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AsmWriteMsr64 (MSR_TURBO_RATIO_LIMIT, Msr.Uint64);
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@endcode
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**/
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#define MSR_TURBO_RATIO_LIMIT 0x000001AD
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/**
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MSR information returned for MSR index #MSR_TURBO_RATIO_LIMIT
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in MaxTurbo 1Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to MaxTurbo 1Core threshold.
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///
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UINT32 MaxTurbo1Core:8;
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///
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/// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in MaxTurbo 2Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to MaxTurbo 2Core threshold and greater than MaxTurbo 1Core threshold.
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///
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UINT32 MaxTurbo2Core:8;
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///
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/// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in MaxTurbo 3Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to MaxTurbo 3Core threshold and greater than MaxTurbo 2Core threshold.
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///
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UINT32 MaxTurbo3Core:8;
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///
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/// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in MaxTurbo 4Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to MaxTurbo 4Core threshold and greater than MaxTurbo 3Core threshold.
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///
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UINT32 MaxTurbo4Core:8;
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///
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/// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in MaxTurbo 5Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to MaxTurbo 5Core and greater than MaxTurbo 4Core threshold.
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///
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UINT32 MaxTurbo5Core:8;
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///
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/// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in MaxTurbo 6Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to MaxTurbo 6Core threshold and greater than MaxTurbo 5Core threshold.
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///
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UINT32 MaxTurbo6Core:8;
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///
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/// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in MaxTurbo 7Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to Group 7 threshold and greater than MaxTurbo 6Core threshold.
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///
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UINT32 MaxTurbo7Core:8;
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///
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/// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in MaxTurbo 8Core
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/// Maximum turbo ratio limit when number of active cores is less or equal
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/// to MaxTurbo 8Core threshold and greater than MaxTurbo 7Core threshold.
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///
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UINT32 MaxTurbo8Core:8;
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} Bits;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_TURBO_RATIO_LIMIT_REGISTER;
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#define PRMRR_MAX_SIZE 0x10000000
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#define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_CORRECTION_FACTOR_19_MHZ 0x2FBA2E26
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#define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_CORRECTION_FACTOR_24_MHZ 0x262E8B52
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#define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_CORRECTION_FACTOR_38_MHZ 0x17DD1713
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#define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_DELAY_VALUE 0x13
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// @todo. Move the definitions to CoreMsrCommon.h
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x000002F4
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#define MSR_UNCORE_PRMRR_PHYS_MASK 0x000002F5
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#define B_MSR_PRMRR_PHYS_MASK_LOCK BIT10
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#define B_MSR_PRMRR_VALID_BIT BIT11
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//. @todo. this alternate msr need to move under fru
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#define MSR_PRMRR_PHYS_BASE_ALT 0x000001F4
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#define MSR_PRMRR_PHYS_MASK_ALT 0x000001F5
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#define B_MSR_PRMRR_BASE_0_CONFIGURED_MASK BIT3
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#define B_CRASHLOG_DUMP_DISABLE BIT0
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#define V_TME_ACTIVATE_TME_POLICY_AES_XTS 0x00
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#define V_TME_ACTIVATE_TME_POLICY_AES_XTS_256 0x02
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#define MSR_BOOT_GUARD_SACM_INFO 0x0000013A
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#define B_BOOT_GUARD_SACM_INFO_NEM_ENABLED BIT0
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#define V_TPM_PRESENT_MASK 0x06
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#define B_BOOT_GUARD_SACM_INFO_TPM_SUCCESS BIT3
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#define B_BOOT_GUARD_SACM_INFO_MEASURED_BOOT BIT5
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#define B_BOOT_GUARD_SACM_INFO_VERIFIED_BOOT BIT6
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#define B_BOOT_GUARD_SACM_INFO_CAPABILITY BIT32
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#define V_CSTATE_LIMIT_C1 0x01
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#define V_CSTATE_LIMIT_C3 0x02
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#define V_CSTATE_LIMIT_C6 0x03
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#define V_CSTATE_LIMIT_C7 0x04
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#define V_CSTATE_LIMIT_C7S 0x05
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#define V_CSTATE_LIMIT_C8 0x06
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#define V_CSTATE_LIMIT_C9 0x07
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#define V_CSTATE_LIMIT_C10 0x08
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#define V_IO_CAPT_LVL2 0x0 ///< C3
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#define V_IO_CAPT_LVL3 0x1 ///< C6
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#define V_IO_CAPT_LVL4 0x2 ///< C7
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#define V_IO_CAPT_LVL5 0x3 ///< C8
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#define V_IO_CAPT_LVL6 0x4 ///< C9
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#define V_IO_CAPT_LVL7 0x5 ///< C10
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#define B_CAP_MSR_HWP_REQ BIT0
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#define MSR_FAST_UNCORE_MSR_CTL_MASK BIT0
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// @todo. use XXX_MSR_FIT_BIOS_ERROR in each generation.
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#define MSR_FIT_BIOS_ERROR 0x000000A5
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#define B_MSR_FIT_BIOS_ERROR_ERROR_CODE_MASK 0x000000FF
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#define N_MSR_FIT_BIOS_ERROR_ENTRY_TYPE_OFFSET 8
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#define B_MSR_FIT_BIOS_ERROR_ENTRY_TYPE_MASK 0x0000FF00
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#define FIT_HEADER_ENTRY 0x0
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#define FIT_SUCCESSFUL 0x0
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#define FIT_SIZE_CHECK 0x1
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#define FIT_RESERVED_FIELD_CHECK 0x2
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#define FIT_VERSION_AND_TYPE_CHECK 0x3
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#define FIT_MICROCODE_UPDATE_ENTRY 0x1
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#define FIT_NO_MICROCODE_UPDATE 0x1
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#define FIT_MICROCODE_UPDATE_FAIL 0x2
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#define FIT_STARTUP_ACM_ENTRY 0x2
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#define FIT_STARTUP_ACM_NOT_SUPPORTED 0x1
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#define FIT_FATAL_ERROR_DURING_ACM 0x2
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#define FIT_CPU_DOES_NOT_SUPPORT_LT 0x3
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#define FIT_BIST_ERRORS 0x4
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#define FIT_BEYOND_END_OF_FIT 0x5
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#define FIT_NO_FIT_ACM_TYPE_MISMATCH 0x6
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#define FIT_ACM_BASE_SIZE_AND_CHECKS 0x7
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#define FIT_GENERAL_CHECKS 0x7F
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#define FIT_DISABLED_BY_CPU 0x1
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#define FIT_POINTER_ERROR 0x2
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#define FIT_FIRST_FIT_ENTRY_MISMATCH 0x3
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#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_OFFSET 0
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#define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_MASK 0x000000000000FFFF
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#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_OFFSET 16
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#define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_MASK 0x000000000000FFFF
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#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_OFFSET 32
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#define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_MASK 0x000000000000FFFF
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#define B_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE BIT62
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#define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE_OFFSET 62
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///
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/// Other defines
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///
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#ifndef CPU_FEATURE_DISABLE
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#define CPU_FEATURE_DISABLE 0
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#endif
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#ifndef CPU_FEATURE_ENABLE
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#define CPU_FEATURE_ENABLE 1
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#endif
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#define CACHE_UNCACHEABLE 0
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#define CACHE_WRITEBACK 6
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#define TXT_PUBLIC_BASE 0xFED30000
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#define R_CPU_BOOT_GUARD_BOOTSTATUS 0xA0
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#define R_CPU_BOOT_GUARD_ACM_STATUS 0x328
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#define R_CPU_ACM_POLICY_STATUS 0x378
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#define MMIO_ACM_POLICY_STATUS (TXT_PUBLIC_BASE + R_CPU_ACM_POLICY_STATUS)
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#define V_CPU_BOOT_GUARD_LOAD_ACM_SUCCESS 0x8000000000000000
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#define B_BOOT_GUARD_ACM_ERRORCODE_MASK 0x00007FF0
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#define B_CPU_BOOT_GUARD_BOOTSTATUS_BLOCK_BOOT_ENABLED BIT0
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#define V_CPU_BOOT_GUARD_BOOTSTATUS_BLOCK_BOOT_ENABLED 0x01
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#define B_CPU_BOOT_GUARD_BOOTSTATUS_S3_TPM_STARTUP_FAILED BIT46
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#define R_CPU_BOOT_GUARD_NEM_MAP_STRUCTURE_ADDRESS 0x320
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//
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// Processor Definitions
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//
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#define CPUID_FULL_STEPPING 0x0000000F
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#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0
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#define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF
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#ifndef STALL_ONE_MICRO_SECOND
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#define STALL_ONE_MICRO_SECOND 1
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#endif
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#ifndef STALL_ONE_MILLI_SECOND
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#define STALL_ONE_MILLI_SECOND 1000
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#endif
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#define BITS(x) (1 << (x))
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/**
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Notes :
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1. Bit position always starts at 0.
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2. Following macros are applicable only for Word aligned integers.
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**/
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#define BIT(Pos, Value) (1 << (Pos) & (Value))
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typedef UINT32 CPU_FAMILY;
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///
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/// Enums for CPU SKU IDs
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///
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typedef enum {
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EnumCpuUlt = 0,
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EnumCpuTrad,
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EnumCpuUlx,
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EnumCpuHalo,
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EnumCpuUnknown
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} CPU_SKU;
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///
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/// Enums for CPU Generation
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///
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typedef enum {
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EnumAdlCpu = 0,
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EnumMtlCpu,
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EnumCpuUnknownGeneration = 255
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} CPU_GENERATION;
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#endif
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