183 lines
7.7 KiB
C
183 lines
7.7 KiB
C
/** @file
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Protocol used to report CPU information
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_INFO_H_
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#define _CPU_INFO_H_
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#include <CpuDataStruct.h>
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#include <CpuLimits.h>
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typedef struct _CPU_INFO_PROTOCOL CPU_INFO_PROTOCOL;
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extern EFI_GUID gCpuInfoProtocolGuid;
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//
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// DXE_CPU_INFO_PROTOCOL revisions
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//
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#define CPU_INFO_PROTOCOL_REVISION 6
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#define CORE_TYPE_NON_HYBRID 0
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#define SMALL_CORE 0
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#define BIG_CORE 1
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#define CORE_TYPE_NUM 2
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//
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// Processor feature definitions.
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//
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#define TXT_SUPPORT BIT0
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#define VMX_SUPPORT BIT1
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#define XD_SUPPORT BIT2
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#define DCA_SUPPORT BIT3
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#define X2APIC_SUPPORT BIT4
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#define AES_SUPPORT BIT5
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#define HT_SUPPORT BIT6
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#define DEBUG_SUPPORT BIT7
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#define DEBUG_LOCK_SUPPORT BIT8
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#define PROC_TRACE_SUPPORT BIT9
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#define HDC_SUPPORT BIT10
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//
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// Max number of VF point offset
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//
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#ifndef CPU_OC_MAX_VF_POINTS
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#define CPU_OC_MAX_VF_POINTS 0xF
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#endif
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#pragma pack(push, 1)
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///
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/// Cache descriptor information
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///
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typedef struct {
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UINT8 Desc; ///< Cache Descriptor
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UINT8 Level; ///< Cache Level
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UINT8 Type; ///< Cache Type. 0: Data, 1: Instruction, 3: Unified
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UINT32 Size; ///< Cache Size.
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UINT16 Associativity; ///< Cache Ways of Associativity.
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} CACHE_DESCRIPTOR_INFO;
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///
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/// Processor information
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///
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typedef struct {
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UINT32 CpuSignature; ///< Processor signature and version information.
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UINT64 Features; ///< Features availability in the CPU based on reading ECX after doing Asmcpuid(EAX=1).
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CHAR8 *BrandString; ///< Processor Brand String.
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UINT8 NumSupportedCores; ///< Total Number of Supported Cores in CPU Package. If Dual core, 2 cores.
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UINT8 NumSupportedThreadsPerCore; ///< Number of Supported Threads per Core.
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UINT8 NumCores; ///< Number of Enabled or Active Cores.
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UINT8 NumHts; ///< Max Number of Enabled Threads per Core. This will be 1 or 2.
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UINT32 IntendedFreq; ///< Maximum non turbo ratio or Config TDP ratio in MHz
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UINT32 ActualFreq; ///< Actual frequency in MHz
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UINT32 Voltage; ///< Current operating voltage.
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CACHE_DESCRIPTOR_INFO *CacheInfo; ///< Cache descriptor information.
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UINT8 MaxCacheSupported; ///< Maximum cache supported.
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UINT8 SmmbaseSwSmiNumber; ///< Software SMI Number from Smbase. @Note: This is unused.
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UINT16 NumberOfPStates; ///< Number of P-States.
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UINT16 NumEnabledThreads; ///< Enabled number of threads.
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UINT8 CoreVfPointCount; ///< The number of Core VF Point.
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UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< OC Ratio for each Core VF Point.
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UINT8 PerCoreRatioOverride; ///< Enable or disable Per Core PState OC supported.
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UINT8 PerCoreRatio[CPU_MAX_BIG_CORES]; ///< Array used to specific max ratio applied to each selected Core.
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UINT8 RingVfPointCount; ///< The number of Ring VF Point.
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UINT8 RingVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< OC Ratio for Ring VF Point.
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} CPU_INFO;
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///
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/// This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA.
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///
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typedef struct {
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EFI_PHYSICAL_ADDRESS LockBoxData; ///< First location (address) of SMRAM CPU DATA.
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EFI_PHYSICAL_ADDRESS SmramCpuData; ///< Second location (Address) of SMRAM CPU DATA.
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UINT64 LockBoxSize; ///< Size of SMRAM CPU DATA.
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} SMRAM_CPU_INFO;
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///
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/// @deprecated due to Non-POR feature
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/// SGX Information
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///
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typedef struct {
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UINT64 SgxSinitNvsData; ///< Sinit SE SVN Version saved and passed back in next boot
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} SGX_INFO;
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#pragma pack(pop)
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///
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/// This protocol provides information about the common features available in this CPU.
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///
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struct _CPU_INFO_PROTOCOL {
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/**
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Revision for the protocol structure.
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Any backwards compatible changes to this protocol will result in an update in the revision number.
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Major changes will require publication of a new protocol
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<b>Revision 1</b>:
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- Initial version
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<b>Revision 2</b>:
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- Add number of enabled threads to CPU_INFO.
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<b>Revision 3</b>:
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- Extend CPU_INFO to support Small Core and Big Core.
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<b>Revision 4</b>:
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- Add Per Core PState OC supported
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New PerCoreRatioOverride and PerCoreRatio
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<b>Revision 5</b>:
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- Add Ring VF point support.
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New RingVfPointCount and Ring per VF Point Ratio.
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<b>Revision 6</b>:
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- Deprecated SGx
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**/
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UINT8 Revision;
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/**
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CPU Supported Feature.
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- BIT0: If set then processor supports TXT.
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- BIT1: If set then processor supports virtual mode extensions.
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- BIT2: If set then processor supports execute disable bit.
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- BIT3: If set then processor supports DCA.
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- BIT4: If set then processor supports X2APIC.
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- BIT5: If set then processor supports Advanced Encryption Standard.
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- BIT6: If set then processor supports hyperthreading.
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- BIT7: If set then processor supports debug interface.
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- BIT8: If set then processor supports debug interface lock.
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- BIT9: If set then processor supports processor trace.
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- BIT10: If Set then processor supports supports HDC.
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**/
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UINT64 CpuCommonFeatures;
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CPU_INFO *CpuInfo; ///< Processor Basic Information Contains Big Core and Small Core
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SMRAM_CPU_INFO *SmramCpuInfo; ///< SMRAM CPU Information
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SGX_INFO *SgxInfo; ///< @deprecated due to Non-POR feature.
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};
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#endif
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