104 lines
6.0 KiB
C
104 lines
6.0 KiB
C
/** @file
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This file contains definitions required for creation of TXT Info HOB.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _TXT_HOB_H_
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#define _TXT_HOB_H_
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#pragma pack(push, 1)
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///
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/// TXT Info data.
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/// The data that will be passed to DXE via TXT_INFO_HOB.
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///
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typedef struct _TXT_INFO_DATA {
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UINT64 SinitMemorySize; ///< Size of memory reserved for placement of SINIT module. This memory is used by MLE.
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UINT64 TxtHeapMemorySize; ///< Size of memory reserved for TXT Heap. This memory is used by MLE.
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EFI_PHYSICAL_ADDRESS TxtDprMemoryBase; ///< Base address of DPR protected memory reserved for Intel TXT component.
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UINT64 TxtDprMemorySize; ///< Size of DPR protected memory reserved for TXT component.
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EFI_PHYSICAL_ADDRESS BiosAcmBase; ///< Base address of BIOS ACM in system firmware.
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UINT64 BiosAcmSize; ///< Size of BIOS ACM.
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EFI_PHYSICAL_ADDRESS SinitAcmBase; ///< Base address of SINIT module if installed in system firmware. Zero otherwise.
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UINT64 SinitAcmSize; ///< Size of SINIT module if installed in system firmware. Zero otherwise.
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UINT64 TgaSize; ///< Size of Trusted Graphics Aperture if supported by chipset.
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EFI_PHYSICAL_ADDRESS TxtLcpPdBase; ///< Base address of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise.
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UINT64 TxtLcpPdSize; ///< Size of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise.
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/**
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Flags passed from BIOS to OS or MRC.
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- BIT0: FLAGS0 for compatible definition.
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- BIT1: TXT_CPU_RESET_REQUIRED for MRC to issue reset if required.
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- BIT2: TPM_INIT_FAILED for indicate TPM initiate status. If the bit set, ResetEstablishmentBit is skipped in Dxe driver.
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**/
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UINT64 Flags;
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EFI_PHYSICAL_ADDRESS ApStartupBase; ///< Base address of AP Startup code
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EFI_PHYSICAL_ADDRESS TsegBase; ///< Physical base address of TSEG region.
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UINT64 TsegSize; ///< Size of the entity at TSEG region.
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EFI_PHYSICAL_ADDRESS MsegBase; ///< Physical base address of MSEG region.
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UINT64 MsegSize; ///< Size of the entity at MSEG region.
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UINT32 AcpiBase:16; ///< Address of PM1a_CNT_BLK register block. It is used by TXT PEIM to clean Sleep Type field of PM1a_CNT_BLK.S4 register before running of SCLEAN.
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UINT32 ChipsetIsTxtCapable:1; ///< Value is set to 1 if chipset is Intel TXT capable.
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UINT32 TxtMode:1; ///< Value is set to 1 if Intel TXT mode is enabled in BIOS Setup.
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UINT32 ResetAux:1; ///< Value is set to 1 if reset Aux is enabled in BIOS Setup.
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UINT32 TxtAcheckRequest:1; ///< Value is set to 1 if TXT Acheck Request is enabled in BIOS Setup.
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UINT32 ProcessorIsTxtCapable:1; ///< Value is set to 1 if processor is Intel TXT capable.
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UINT32 Reserved:11; ///< Reserved for future use
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UINT8 AcmMajorVersion; ///< BIOSACM binary major version
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UINT8 AcmMinorVersion; ///< BIOSACM binary minor version
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UINT8 AcmRevision; ///< BIOSACM binary revision
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// Since the biggest element is UINT64, this structure should be aligned with 64 bits.
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UINT8 Rsvd[1]; ///< Reserved for config block alignment.
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} TXT_INFO_DATA; ///< TXT info
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// Flags passed from BIOS to OS or MRC.
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#define FLAGS0 0x1 ///< BIT0: FLAGS0 for compatible definition.
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#define TXT_CPU_RESET_REQUIRED 0x2 ///< BIT1: TXT_CPU_RESET_REQUIRED for MRC to issue reset if required.
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#define TPM_INIT_FAILED 0x4 ///< BIT2: TPM_INIT_FAILED for indicate TPM initiate status.
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///< If the bit set, ResetEstablishmentBit is skipped in Dxe driver.
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///
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/// HOB to save TXT Info data.
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/// TXT Info HOB is used for passing Policy settings and CPU/chipset information within TXT modules.
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///
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typedef struct _TXT_INFO_HOB {
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< EFI Hob Guid Type.
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TXT_INFO_DATA Data; ///< TXT Info Data.
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} TXT_INFO_HOB; ///< TXT Info HOB
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#pragma pack(pop)
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#endif
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