537 lines
17 KiB
C
537 lines
17 KiB
C
/** @file
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SMM IO/MSR bitmap support functions
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "SmmCpuFeatures.h"
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#include "SmmResourceConfig.h"
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#define HIGH_MSR_BASE 0xC0000000
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#define IO_BITMAP_BUFFER_LENGTH 0x2000
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#define MSR_BITMAP_BUFFER_LENGTH 0x1000
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#define TSS_SEGMENT 0x70
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#define TSS_IOMAP_OFFSET 102
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EFI_HANDLE mSmmResourceProtectHandle = NULL;
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BOOLEAN mLockSmmResourceControl = FALSE;
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UINTN *mIoBitMapBase;
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BOOLEAN mSmmResourceConfigApiInitialized = FALSE;
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extern UINTN gMsrBitMapBase;
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UINT32 mMsrIndex[] = {
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MSR_IA32_SYSENTER_CS,
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MSR_IA32_SYSENTER_ESP,
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MSR_IA32_SYSENTER_EIP,
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MSR_IA32_STAR,
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MSR_IA32_LSTAR,
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MSR_IA32_FMASK,
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MSR_IA32_PERF_GLOBAL_CTRL,
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};
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//
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// SMM Resource (IO, MSR) Config protocol Interfaces.
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//
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GLOBAL_REMOVE_IF_UNREFERENCED
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SMM_RESOURCE_CONFIG_PROTOCOL mSmmResourceConfigProtocol = {
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ConfigIoBitmap,
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ConfigMsrBitmap,
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InstallIoBitmap,
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InstallMsrBitmap
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};
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/**
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Allocate pages for code.
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@param[in] Pages Number of pages to be allocated.
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@return Allocated memory.
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**/
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VOID *
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AllocateCodePages (
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IN UINTN Pages
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);
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/**
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SMM End Of Dxe event notification handler.
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Setting Global variable to notify End Of Dxe Event to control SMM Resource access
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@param[in] Protocol Points to the protocol's unique identifier
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@param[in] Interface Points to the interface instance
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@param[in] Handle The handle on which the interface was installed
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@retval EFI_SUCCESS Notification handler runs successfully.
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**/
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EFI_STATUS
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EFIAPI
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SpsSmmEndOfDxeEventNotify (
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IN CONST EFI_GUID *Protocol,
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IN VOID *Interface,
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IN EFI_HANDLE Handle
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)
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{
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DEBUG ((DEBUG_INFO, "SpsSmmEndOfDxeEventNotify\n"));
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mLockSmmResourceControl = TRUE;
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return EFI_SUCCESS;
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}
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/**
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This function installs protocol interface for IO, MSR Configuration.
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@retval EFI_SUCCESS Successfully installed SMM Resource Config APIs.
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**/
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EFI_STATUS
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EFIAPI
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SpsSmmResourceConfigApiInit (
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VOID
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)
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{
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EFI_STATUS Status;
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VOID *Registration;
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//
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// Install Protocol for SMM Resource config APIs
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//
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Status = gSmst->SmmInstallProtocolInterface (
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&mSmmResourceProtectHandle,
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&gSmmResourceConfigProtocolGuid,
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EFI_NATIVE_INTERFACE,
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&mSmmResourceConfigProtocol
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);
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ASSERT_EFI_ERROR(Status);
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//
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// Register SMM End of DXE Event
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//
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Status = gSmst->SmmRegisterProtocolNotify (
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&gEfiSmmEndOfDxeProtocolGuid,
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SpsSmmEndOfDxeEventNotify,
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&Registration
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);
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ASSERT_EFI_ERROR(Status);
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return Status;
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}
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/**
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Sub function for Configuring IO Port access for selected CPU.
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@param[in] IoBitMapBase IO Bit map base address
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@param[in] Port Port address
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@param[in] DenyRwAccess TRUE = Deny access to port; FALSE = Allow access.
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**/
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VOID
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InternalProtectIo (
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IN UINTN IoBitMapBase,
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IN UINT16 Port,
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IN BOOLEAN DenyRwAccess
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)
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{
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UINT8 *IoBitmap;
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UINTN Index;
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UINTN Offset;
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if (Port >= 0x8000) {
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IoBitmap = (UINT8 *) (UINTN) (IoBitMapBase + SIZE_4KB);
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Port -= 0x8000;
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} else {
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IoBitmap = (UINT8 *) (UINTN) (IoBitMapBase);
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}
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Index = Port / 8;
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Offset = Port % 8;
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if (DenyRwAccess) {
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IoBitmap[Index] |= (UINT8)(1 << Offset);
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} else {
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IoBitmap[Index] &= (UINT8)~(1 << Offset);
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}
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return;
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}
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/**
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This function configures IO port access through bitmap for all CPUs within SMM.
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ie Using this API, IO port can be configured as read write access or restricted access
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within SMM.
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For example: To revoke access to IO port 0xCF8 to 0xCFB, invoke this API with
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PortBase = 0xCF8, PortLength = 4 and DenyRwAccess = TRUE
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@param[in] PortBase IO Port base address.
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@param[in] PortLength Length of IO Port bitmap that needs access configuration.
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@param[in] DenyRwAccess 0 = Allow RW Access to port; 1 = Deny RW Access to port.
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@retval EFI_SUCCESS Successfully enabled protection for specified IO range.
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**/
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EFI_STATUS
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EFIAPI
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ConfigIoBitmap (
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IN UINT16 PortBase,
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IN UINT16 PortLength,
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IN BOOLEAN DenyRwAccess
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)
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{
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UINTN CpuIndex;
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UINTN Index;
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if (mLockSmmResourceControl) {
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return EFI_ACCESS_DENIED;
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}
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for (CpuIndex = 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) {
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for (Index = 0; Index < PortLength; Index++) {
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InternalProtectIo (mIoBitMapBase[CpuIndex], (UINT16)(PortBase + Index), DenyRwAccess);
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}
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}
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return EFI_SUCCESS;
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}
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/**
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This function configures MSR access through bitmap for all CPUs within SMM.
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Using this API, any MSR can be configured as Read only, Write only, Read/Write
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or no access with in SMM.
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For example:
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To configure MSR 0xE2, Invoke this API with MSR = 0xE2 and
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Case1: To revoke both read and write access
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DenyReadAccess = TRUE, DenyWriteAccess = TRUE.
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Case2: To revoke read access and allow Write access
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DenyReadAccess = TRUE, DenyWriteAccess = FALSE.
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Case3: To allow read access and revoke write access
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DenyReadAccess = FALSE, DenyWriteAccess = TRUE.
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Case4: To allow both read and Write access
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DenyReadAccess = FALSE, DenyWriteAccess = FALSE.
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DGR reference code allows access for only specified MSRs and denies
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access to rest of all MSRs. Refer mAllowedListMsr table structure at
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Intel\<Platform Sample Pkg>\Features\NiftyRock\PpamPlatformSmm\SmmIoMsrAccess.h for
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list of MSRs allowed for R/W access.
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OEM platform SMM driver can use this API to modify access to any MSR before
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SMM End of Dxe event (gEfiSmmEndOfDxeProtocolGuid).
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@param[in] Msr MSR base address.
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@param[in] DenyReadAccess FALSE - Allow read access, TRUE - Deny read access to MSR.
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@param[in] DenyWriteAccess FALSE - Allow write access, TRUE - Deny write access to MSR.
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@retval EFI_SUCCESS MSR Bitmap has been successfully configured.
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@retval EFI_INVALID_PARAMETER If MSR is not in the range of 0 to 0x1FFF and
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0xC0000000 to 0xC0001FFF.
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@retval EFI_ACCESS_DENIED If this protocol is invoked after SMM End of Dxe event.
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**/
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EFI_STATUS
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EFIAPI
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ConfigMsrBitmap (
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IN UINT32 Msr,
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IN BOOLEAN DenyReadAccess,
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IN BOOLEAN DenyWriteAccess
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)
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{
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UINT8 *MsrBitmap;
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UINTN Index;
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UINTN Offset;
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if (mLockSmmResourceControl) {
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return EFI_ACCESS_DENIED;
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}
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MsrBitmap = (UINT8 *) (UINTN) (gMsrBitMapBase);
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if (Msr >= HIGH_MSR_BASE) {
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Msr = Msr - HIGH_MSR_BASE + 0x2000;
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}
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//
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// Configure MSR Read access
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//
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Index = Msr / 8;
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Offset = Msr % 8;
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if (DenyReadAccess) {
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MsrBitmap[Index] |= (UINT8)(1 << Offset);
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}
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else {
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MsrBitmap[Index] &= (UINT8)~(1 << Offset);
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}
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//
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// Configure MSR Write access
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//
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Msr = Msr + 0x4000;
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Index = Msr / 8;
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Offset = Msr % 8;
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if (DenyWriteAccess) {
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MsrBitmap[Index] |= (UINT8)(1 << Offset);
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}
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else {
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MsrBitmap[Index] &= (UINT8)~(1 << Offset);
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}
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return EFI_SUCCESS;
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}
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/**
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This function allows a caller to install new IO Bitmap on top of the
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default IO Bitmap.
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@param[in] Buffer Buffer address of IO Bitmap.
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@param[in] BufferLength Length of the buffer. This should be 0x2000.
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@retval EFI_SUCCESS IO bitmap has been successfully installed.
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@retval EFI_INVALID_PARAMETER Buffer length is not equal to 0x2000 (8KB).
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@retval EFI_ACCESS_DENIED This protocol is invoked after SMM End of Dxe event.
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**/
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EFI_STATUS
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EFIAPI
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InstallIoBitmap (
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IN UINTN *Buffer,
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IN UINT16 BufferLength
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)
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{
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UINTN CpuIndex;
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UINT8 *IoBitmap;
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if (BufferLength != IO_BITMAP_BUFFER_LENGTH) {
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DEBUG ((DEBUG_ERROR, "Invalid Buffer Length \n"));
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return EFI_INVALID_PARAMETER;
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}
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if (mLockSmmResourceControl) {
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return EFI_ACCESS_DENIED;
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}
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for (CpuIndex = 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) {
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IoBitmap = (UINT8 *) (UINTN) (mIoBitMapBase [CpuIndex]);
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CopyMem (IoBitmap, (UINT8 *) Buffer, BufferLength);
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}
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return EFI_SUCCESS;
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}
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/**
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This function allows a caller to install new MSR Bitmap on top of the
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default MSR Bitmap.
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@param[in] Buffer Buffer address of IO Bitmap.
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@param[in] BufferLength Length of the buffer. This should be 0x1000.
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@retval EFI_SUCCESS MSR bitmap has been successfully installed.
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@retval EFI_INVALID_PARAMETER Buffer length is not equal to 0x1000 (4KB).
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@retval EFI_ACCESS_DENIED This protocol is invoked after SMM End of Dxe event.
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**/
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EFI_STATUS
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EFIAPI
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InstallMsrBitmap (
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IN UINTN *Buffer,
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IN UINT16 BufferLength
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)
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{
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UINT8 *MsrBitmap;
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if (BufferLength != MSR_BITMAP_BUFFER_LENGTH) {
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DEBUG((DEBUG_ERROR, "Invalid Buffer Length \n"));
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return EFI_INVALID_PARAMETER;
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}
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if (mLockSmmResourceControl) {
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return EFI_ACCESS_DENIED;
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}
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MsrBitmap = (UINT8 *) (UINTN) (gMsrBitMapBase);
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CopyMem (MsrBitmap, (UINT8 *) Buffer, BufferLength);
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return EFI_SUCCESS;
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}
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/**
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Initialize IO MSR Bitmap
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Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0):
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EAX Bits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if EAX[n] is 1.
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Bit 00: x87 state.
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Bit 01: SSE state.
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Bit 02: AVX state.
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Bits 04 - 03: MPX state.
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Bits 07 - 05: AVX-512 state.
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Bit 08: Used for IA32_XSS.
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Bit 09: PKRU state.
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Bits 31 - 10: Reserved.
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EBX Bits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by
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enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area
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are not enabled.
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ECX Bit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the
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XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in
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XCR0.
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EDX Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if EDX[n] is 1.
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Bits 31 - 00: Reserved.
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Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
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EAX Bit 00: XSAVEOPT is available.
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Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
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Bit 02: Supports XGETBV with ECX = 1 if set.
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Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
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Bits 31 - 04: Reserved.
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EBX Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
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ECX Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be
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set to 1 only if ECX[n] is 1.
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Bits 07 - 00: Used for XCR0.
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Bit 08: PT state.
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Bit 09: Used for XCR0.
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Bits 31 - 10: Reserved.
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EDX Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can
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be set to 1 only if EDX[n] is 1.
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Bits 31 - 00: Reserved.
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Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)
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NOTES:
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Leaf 0DH output depends on the initial value in ECX.
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Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the
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XCR0 register or the IA32_XSS MSR.
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* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 <= n <= 31) is invalid
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if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if
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sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
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EAX Bits 31 - 0: The size in bytes (from the offset specified in EBX) of the save area for an extended state
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feature associated with a valid sub-leaf index, n.
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EBX Bits 31 - 0: The offset in bytes of this extended state component's save area from the beginning of the
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XSAVE/XRSTOR area.
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This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.
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ECX Bit 00 is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear
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if bit n is instead supported in XCR0.
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Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component
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located on the next 64-byte boundary following the preceding state component (otherwise, it is located
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immediately following the preceding state component).
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Bits 31 - 02 are reserved. This field reports 0 if the sub-leaf index, n, is invalid*.
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EDX This field reports 0 if the sub-leaf index, n, is invalid*; otherwise it is reserved.
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@param[in] CpuIndex CPU Index no.
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@param[in] GdtBase GDT Base address
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@param[in] GdtSize GDT size
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**/
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EFI_STATUS
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EFIAPI
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InitializeIoMsrBitmap (
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IN UINTN CpuIndex,
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IN UINTN GdtBase,
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IN UINTN GdtSize
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)
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{
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EFI_STATUS Status = EFI_SUCCESS;
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IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
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UINTN TssBase;
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UINTN IoMapOffset;
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UINT32 Eax;
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UINT32 Ebx;
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UINT32 Ecx;
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UINT32 Edx;
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UINT32 Index;
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UINT64 Xcr0;
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TssBase = 0;
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IoMapOffset = 0;
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if (gMsrBitMapBase == 0) {
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gMsrBitMapBase = (UINTN) AllocateCodePages (1);
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ASSERT(gMsrBitMapBase != 0);
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}
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if (gMsrBitMapBase != 0) {
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//
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// Fill all bits in the MSR bitmap field with 1 to Deny access for R/W.
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// Only required MSR access will be enabled by clearing its corresponding bit from Platform Pkg.
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//
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SetMem ((VOID *)gMsrBitMapBase, EFI_PAGES_TO_SIZE(1), 0xFF);
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}
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if (mIoBitMapBase == NULL) {
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mIoBitMapBase = AllocateCodePages (EFI_SIZE_TO_PAGES(sizeof(UINTN) * PcdGet32(PcdCpuMaxLogicalProcessorNumber)));
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if (mIoBitMapBase != NULL) {
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ZeroMem ((VOID *) mIoBitMapBase, sizeof (UINTN)* PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
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} else {
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ASSERT(mIoBitMapBase != NULL);
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return EFI_OUT_OF_RESOURCES;
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}
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}
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DEBUG ((DEBUG_INFO, "GDTBase(%d) - 0x%x, ", CpuIndex, GdtBase));
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GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(GdtBase + TSS_SEGMENT);
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TssBase = GdtDescriptor->Bits.BaseLow + (GdtDescriptor->Bits.BaseMid << 16) + (GdtDescriptor->Bits.BaseHigh << 24);
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IoMapOffset = *(UINTN *) (TssBase + TSS_IOMAP_OFFSET);
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mIoBitMapBase[CpuIndex] = TssBase + IoMapOffset;
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//
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// Fill all bits in the bitmap field with 1 to Deny access for R/W.
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|
// Only required IO Port access will be enabled by clearing its corresponding bit from Platform Pkg.
|
|
//
|
|
SetMem ((VOID *) (TssBase + IoMapOffset), 0x2000, 0xFF);
|
|
DEBUG ((DEBUG_INFO, "mIoBitMapBase(%d) - 0x%x\n", CpuIndex, mIoBitMapBase[CpuIndex]));
|
|
|
|
if (CpuIndex == 0) {
|
|
Xcr0 = 3;
|
|
for (Index = 0; Index < 64; Index++) {
|
|
if ((LShiftU64 (1, Index) & Xcr0) == 0) {
|
|
continue;
|
|
}
|
|
AsmCpuidEx (
|
|
0xD,
|
|
Index,
|
|
&Eax,
|
|
&Ebx,
|
|
&Ecx,
|
|
&Edx
|
|
);
|
|
if (Index == 0) {
|
|
Xcr0 = Eax | LShiftU64 (Edx, 32);
|
|
}
|
|
DEBUG ((DEBUG_INFO, "CPUID (0xD, %d) - 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", Index, Eax, Ebx, Ecx, Edx));
|
|
}
|
|
}
|
|
|
|
if (!mSmmResourceConfigApiInitialized) {
|
|
Status = SpsSmmResourceConfigApiInit ();
|
|
mSmmResourceConfigApiInitialized = TRUE;
|
|
}
|
|
|
|
return Status;
|
|
}
|