274 lines
7.3 KiB
C
274 lines
7.3 KiB
C
/** @file
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The CPU specific programming for PiSmmCpuDxeSmm module.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2010 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef __SMM_FEATURES_H__
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#define __SMM_FEATURES_H__
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#include <PiSmm.h>
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#include <Protocol/SmmAccess2.h>
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#include <Protocol/SmmCpuService.h>
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#include <Protocol/CpuPolicyProtocol.h>
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#include <Library/SmmCpuFeaturesLib.h>
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#include <Library/PcdLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/LocalApicLib.h>
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#include <Library/SynchronizationLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/MtrrLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesLib.h>
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#include <Library/CpuCommonLib.h>
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#include <Register/Cpuid.h>
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#include <Register/Msr.h>
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#include <Register/ArchMsr.h>
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#include <Register/CommonMsr.h>
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#include <Library/HobLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <Library/CpuInfoFruLib.h>
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#include <Library/CpuExceptionHandlerLib.h>
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#include <Library/PeCoffGetEntryPointLib.h>
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#include <Library/MsrFruLib.h>
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#include "SmmPpam.h"
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#include "SmmSps.h"
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#define SUPERVISOR_PAGE_NUM 2
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#define PROTECT_MODE_CS 0x8
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#define SMMSEG_PROTECT_MODE_CS 0x10
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#define SMMSEG_PROTECT_MODE_DS 0x18
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#define PROTECT_MODE_DS 0x20
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#define REAL_MODE_CS 0x28
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#define REAL_MODE_DS 0x30
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#define LONG_MODE_CS 0x38
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#define LONG_MODE_DS 0x40
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#define R3_CS_32 0x48
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#define R3_DS_32 0x50
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#define R3_CS 0x58
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#define R3_DS 0x60
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#define TSS_SEGMENT 0x70
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//
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// CET definition
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//
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#define CPUID_CET_SS BIT7
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#define CPUID_CET_IBT BIT20
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#define CR4_CET_ENABLE BIT23
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#define CPUID1_EDX_XD_SUPPORT 0x100000
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#define CR0_WP BIT16
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//
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// Define for Protected Mode SMM Entry Template
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//
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#define SMMSEG_PROTECT_MODE_CODE_SEGMENT 0x10
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#pragma pack(1)
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typedef struct {
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UINT16 Limit;
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UINT32 Base;
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} IA32_PROT_DESCRIPTOR;
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#pragma pack()
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////////
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// Below section is definition for CPU SMM Feature context
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////////
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//
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// Structure to describe CPU_SMM_FEATURE_CONTEXT
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//
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typedef struct {
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BOOLEAN SmrrEnabled;
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BOOLEAN Smrr2Enabled;
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} CPU_SMM_FEATURE_CONTEXT;
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//
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// SMMSEG_FEATURE_ENABLES bitmap
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//
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#define SMMSEG_FEATURE_ENABLE BIT0
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#define SMMSEG_FEATURE_CR4_MCE_CTL_ENABLE BIT1
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//
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// Structure to describe CPU SMM Protected Mode
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//
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typedef struct {
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UINT32 Reserved1;
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UINT32 SmmSegFeatureEnables; // SMM_SEG_FEATURE_ENABLES
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UINT32 GDTRLimit;
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UINT32 GDTRBaseOffset;
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UINT32 CSSelector;
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UINT32 Reserved3;
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UINT32 ESPOffset;
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UINT32 Reserved4;
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UINT32 IDTRLimit;
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UINT32 IDTRBaseOffset;
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} SMMSEG;
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#define SMM_PROT_MODE_GDT_ENTRY_COUNT 27
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//
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// SMM PROT MODE CONTEXT (total 0x100 bytes)
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//
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typedef struct {
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SMMSEG SmmProtectedModeSMMSEG; // 40 bytes
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IA32_SEGMENT_DESCRIPTOR SmmProtectedModeGdt[SMM_PROT_MODE_GDT_ENTRY_COUNT]; // 27 * 8 = 216 bytes
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} SMM_PROT_MODE_CONTEXT;
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//
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// SMM CPU synchronization features available on a processor
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//
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typedef struct {
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BOOLEAN TargetedSmiSupported;
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BOOLEAN DelayIndicationSupported;
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BOOLEAN BlockIndicationSupported;
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//
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// This processor's LOG_PROC_EN bit used in SMM_ENABLE, SMM_DELAYED, and SMM_BLOCKED MSRs
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// (introduced in Haswell processor).
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// Value of "-1" indicates this field is invalid (i.e. LOG_PROC_EN bit is not
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// supported)
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//
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UINT64 HaswellLogProcEnBit;
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} SMM_CPU_SYNC_FEATURE;
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///
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///
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///
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extern BOOLEAN mSaveStateInMsr;
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extern BOOLEAN mSmmInitSaveStateInMsr;
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extern UINT8 mSmmFeatureSaveStateRegisterLma;
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extern SPIN_LOCK *mMsrSpinLock;
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extern BOOLEAN mSmmPpamEnable;
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extern BOOLEAN mSmmProcTraceEnable;
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extern UINT64 gSmmSupovrStateLockData;
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/**
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Read MSR or CSR based on the CPU type Register to read.
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NOTE: Since platform may uses I/O ports 0xCF8 and 0xCFC to access
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CSR, we need to use SPIN_LOCK to avoid collision on MP System.
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@param[in] CpuIndex The processor index.
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@param[in] RegName Register name.
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@return 64-bit value read from register.
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**/
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UINT64
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SmmReadReg64 (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName
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);
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/**
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Write MSR or CSR based on the CPU type Register to write.
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NOTE: Since platform may uses I/O ports 0xCF8 and 0xCFC to access
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CSR, we need to use SPIN_LOCK to avoid collision on MP System.
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@param[in] CpuIndex The processor index.
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@param[in] RegName Register name.
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@param[in] RegValue 64-bit Register value.
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**/
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VOID
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SmmWriteReg64 (
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IN UINTN CpuIndex,
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IN SMM_REG_NAME RegName,
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IN UINT64 RegValue
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);
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/**
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Initialize SMM Protected Mode IDT table.
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@param[in] Cr3 CR3 value.
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**/
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VOID
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InitProtectedModeIdt (
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IN UINT32 Cr3
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);
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/**
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Allocate pages for code.
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@param[in] Pages Number of pages to be allocated.
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@return Allocated memory.
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**/
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VOID *
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SmmFeatureAllocateCodePages (
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IN UINTN Pages
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);
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/**
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This function sets SmmSupovrStateLock MSR.
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NOTE: This function does not take effect before
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SmmCpuFeaturesCompleteSmmReadyToLock().
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**/
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VOID
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EFIAPI
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SmmSupovrStateLock (
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VOID
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);
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/**
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This function initializes CPU Shadow Stack.
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@param[in] CpuIndex The processor index.
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@param[in] ShadowStack A pointer to Shadow Stack.
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**/
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VOID
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SmmCpuFeaturesInitShadowStack (
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IN UINTN CpuIndex,
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IN VOID *ShadowStack
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);
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/**
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This function fixes up the address of the global variable or function
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referred in SmiEntry assembly files to be the absoute address.
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**/
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VOID
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EFIAPI
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SmmCpuFeaturesLibSmiEntryFixupAddress (
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VOID
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);
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#endif
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