381 lines
11 KiB
C
381 lines
11 KiB
C
/** @file
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PEIM to initialize the cache and program for unlock processor
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification
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**/
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#include <Ppi/MasterBootMode.h>
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#include <Library/DebugLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/HobLib.h>
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#include <Ppi/SecPlatformInformation.h>
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#include <Library/ReportStatusCodeLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include "CpuInitPeim.h"
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#include <Library/CpuPlatformLib.h>
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#include <Library/TxtPeiLib.h>
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#include <Library/CpuCommonLib.h>
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#include <Library/CpuInitLib.h>
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#include <Library/ConfigBlockLib.h>
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#include <Library/PeiOcLib.h>
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#include <Library/CpuPowerOnConfigLib.h>
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#include <Library/PostCodeLib.h>
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#include <Library/PcdLib.h>
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#include <Register/Cpuid.h>
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#include <Register/ArchitecturalMsr.h>
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#include <Register/ArchMsr.h>
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#include <Library/MsrFruLib.h>
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#include <Library/CpuInfoFruLib.h>
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#include <Library/PeiCpuInitFruLib.h>
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extern EFI_GUID gHtBistHobGuid;
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#if FixedPcdGetBool(PcdFspBinaryEnable) == 0
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STATIC EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
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{
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiMasterBootModePpiGuid,
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BuildBistHob
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}
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};
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#endif
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/**
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Check some CPU policies are valid for debugging unexpected problem if these
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values are not initialized or assigned incorrect resource.
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@param[in] SiPreMemPolicy The Si PreMem Policy protocol instance
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**/
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VOID
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CpuValidatePolicy (
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IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy
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)
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{
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ASSERT (SiPreMemPolicy->TableHeader.Header.Revision == SI_PREMEM_POLICY_REVISION);
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}
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/**
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Check on the processor if Debug Interface is supported
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@retval TRUE DebugInterface is supported.
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@retval FALSE DebugInterface is not supported.
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**/
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BOOLEAN
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IsDebugInterfaceSupported (
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VOID
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)
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{
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BOOLEAN Support;
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CPUID_VERSION_INFO_ECX CpuidVersionInfoEcx;
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Support = FALSE;
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///
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/// Debug interface is supported if CPUID (EAX=1): ECX[11] = 1,
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///
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AsmCpuid (
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CPUID_VERSION_INFO,
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NULL,
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NULL,
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&CpuidVersionInfoEcx.Uint32,
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NULL
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);
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if (CpuidVersionInfoEcx.Bits.SDBG == 1) {
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Support = TRUE;
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}
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return Support;
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}
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/**
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Enable/Disable Debug Interfaces in the processor.
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@param[in] Support - To enable or disable Debug Interface feature.
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@retval VOID - No value to return
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**/
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VOID
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EnableDisableDebugInterface (
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IN UINTN Support
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)
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{
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MSR_IA32_DEBUG_INTERFACE_REGISTER DebugInterfaceReg;
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///
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/// Check if the processor supports debug interface
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///
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DebugInterfaceReg.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
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if (!(DebugInterfaceReg.Bits.Lock)) {
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if (Support) {
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///
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/// Enable Debug Interface (MSR 0xC80.Bit0 = 1)
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///
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DebugInterfaceReg.Bits.Enable = 1;
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} else {
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///
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/// Disable Debug Interface (MSR 0xC80.Bit0 = 0)
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///
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DebugInterfaceReg.Bits.Enable = 0;
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}
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AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, DebugInterfaceReg.Uint64);
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}
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}
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/**
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Lock Debug Interface in the processor.
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@param[in] Support - To lock Debug Interface feature.
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@retval VOID - No value to return
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**/
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VOID
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LockDebugInterface (
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)
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{
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MSR_IA32_DEBUG_INTERFACE_REGISTER DebugInterfaceReg;
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///
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/// Check if the processor supports debug interface
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///
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DebugInterfaceReg.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
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if (!(DebugInterfaceReg.Bits.Lock)) {
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DebugInterfaceReg.Bits.Lock = 1;
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AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, DebugInterfaceReg.Uint64);
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}
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}
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/**
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This function performs basic initialization for CPU in PEI phase after Policy produced.
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Enable/Disable CPU Debug as per Setup and locks it.
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@param[in] SiPreMemPolicyPpi The Si Pre-Mem Policy PPI instance
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**/
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EFI_STATUS
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CpuOnPolicyInstalled (
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IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
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)
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{
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EFI_STATUS Status;
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CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
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CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
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DEBUG ((DEBUG_INFO, "CpuOnPolicyInstalled Start \n"));
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PostCode (0xC20);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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#if FixedPcdGetBool(PcdFspBinaryEnable) == 0
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///
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/// Install Notify
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///
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Status = PeiServicesNotifyPpi (&mNotifyList[0]);
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ASSERT_EFI_ERROR (Status);
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#endif
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DEBUG ((DEBUG_INFO, "XmmInit Start \n"));
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PostCode (0xC2F);
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///
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/// Init XMM support
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///
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XmmInit ();
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IsValiduCodeEntry ();
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///
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/// Initializes TXT after Policy PPI produced
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///
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DEBUG ((DEBUG_INFO, "TxtInit Start \n"));
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PostCode (0xC3F);
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TxtInit ();
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if (CpuSecurityPreMemConfig->SkipStopPbet != TRUE) {
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///
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/// Disable PBET
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///
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StopPbeTimer ();
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}
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///
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/// Init CPU Straps
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///
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PostCode (0xC4F);
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///
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/// SSC Configuration
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///
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DEBUG ((DEBUG_INFO, "Invoking PeiCpuSscConfigPreMem \n"));
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PeiCpuSscConfigPreMem ((BOOLEAN)CpuConfigLibPreMemConfig->ComputeDieSscEnable, (BOOLEAN)CpuConfigLibPreMemConfig->SocDieSscEnable, CpuConfigLibPreMemConfig->ComputeDieSscValue, CpuConfigLibPreMemConfig->SocDieSscValue);
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if (!IsSimicsEnvironment ()) {
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SetCpuStrapAndEarlyPowerOnConfig (SiPreMemPolicyPpi);
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}
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//
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// Enable/Disable CPU Debug MSR as per setup and Lock Before Enabling TME (TME is being activated in Memory Init - MrcDone function)
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// If TME is enabled and not in Debug mode, then CPU Debug must be disabled and Locked.
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//
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DEBUG ((DEBUG_INFO, "Invoking LockEnableDisableCpuDebug \n"));
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if (IsDebugInterfaceSupported ()) {
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if (CpuConfigLibPreMemConfig->DebugInterfaceEnable < 2) {
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EnableDisableDebugInterface (CpuConfigLibPreMemConfig->DebugInterfaceEnable);
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}
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if (CpuConfigLibPreMemConfig->DebugInterfaceLockEnable == 1) {
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LockDebugInterface ();
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}
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}
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//
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// Program Crashlog setting at PreMem phase
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//
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PeiCpuCrashLogMailboxEnable ((BOOLEAN)(CpuConfigLibPreMemConfig->CrashLogEnable));
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DEBUG ((DEBUG_INFO, "CPU Pre-Mem Exit \n"));
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PostCode (0xC6F);
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return EFI_SUCCESS;
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}
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#if FixedPcdGetBool(PcdFspBinaryEnable) == 0
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/**
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Build BIST HOB
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@param[in] PeiServices - Indirect reference to the PEI Services Table.
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@param[in] NotifyDescriptor - Address of the notification descriptor data structure. Type
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EFI_PEI_NOTIFY_DESCRIPTOR is defined above.
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@param[in] Ppi - Address of the PPI that was installed.
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@retval EFI_SUCCESS - Hob built or not necessary
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**/
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EFI_STATUS
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EFIAPI
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BuildBistHob (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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)
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{
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EFI_STATUS Status;
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EFI_BOOT_MODE BootMode;
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EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformInformationPpi;
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UINT64 InformationSize;
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EFI_SEC_PLATFORM_INFORMATION_RECORD *SecPlatformInformation;
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BIST_HOB_DATA BspBistData;
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VOID *Hob;
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SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
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UINT32 BistStatus;
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CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
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Status = PeiServicesGetBootMode (&BootMode);
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if (!EFI_ERROR (Status) && (BootMode == BOOT_ON_S3_RESUME)) {
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return EFI_SUCCESS;
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}
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Status = PeiServicesLocatePpi (
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&gEfiSecPlatformInformationPpiGuid, // GUID
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0, // Instance
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NULL, // EFI_PEI_PPI_DESCRIPTOR
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(VOID ** ) &SecPlatformInformationPpi // PPI
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);
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if (Status == EFI_NOT_FOUND) {
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return EFI_SUCCESS;
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}
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = PeiServicesLocatePpi (
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&gSiPreMemPolicyPpiGuid,
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0,
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NULL,
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(VOID **) &SiPreMemPolicyPpi
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);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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///
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/// Obtain BIST information for BSP. Information for APs will obtained in DXE phase during MP initialization.
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///
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ZeroMem (&BspBistData, sizeof (BIST_HOB_DATA));
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SecPlatformInformation = (EFI_SEC_PLATFORM_INFORMATION_RECORD *) (&(BspBistData.Health));
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InformationSize = sizeof (BspBistData.Health);
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Status = SecPlatformInformationPpi->PlatformInformation (
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(CONST EFI_PEI_SERVICES **) PeiServices,
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&InformationSize,
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SecPlatformInformation
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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///
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/// Dump BIST information to serial log
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///
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BistStatus = SecPlatformInformation->x64HealthFlags.Uint32;
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DEBUG ((DEBUG_INFO, "BistStatus = 0x%x\n", BistStatus));
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if (BistStatus != 0) {
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DEBUG ((DEBUG_ERROR, "BIST for BSP failed\n"));
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ReportStatusCode (
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EFI_ERROR_MAJOR | EFI_ERROR_CODE,
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EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST
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);
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ASSERT (FALSE);
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} else if (CpuConfigLibPreMemConfig->BistOnReset == 1) {
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DEBUG ((DEBUG_INFO, "BIST for BSP passed\n"));
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}
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BspBistData.ApicId = GetCpuApicId ();
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Hob = BuildGuidDataHob (
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&gHtBistHobGuid,
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&BspBistData,
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sizeof (BIST_HOB_DATA)
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);
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ASSERT (Hob != NULL);
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return Status;
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}
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#endif
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