427 lines
16 KiB
C
427 lines
16 KiB
C
/** @file
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This file contains power management C State configuration functions for
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processors.
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Acronyms:
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- PPM: Processor Power Management
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- TM: Thermal Monitor
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- IST: Intel(R) Speedstep technology
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- HT: Hyper-Threading Technology
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2012 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification
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**/
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#include "PowerMgmtCommon.h"
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/**
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Initializes C States Power management features
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**/
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VOID
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InitCState (
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VOID
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)
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{
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///
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/// Initialize C states, some are general, some are processor specific.
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///
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/// AcpiIoBase + 0x14 (PM_CST_LVL2) register no longer exists in PCH.
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/// When the IO in this range is read, the CPU puts itself into a mwait
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/// and does not forward this IO to the PCH. MSR_PMG_IO_CAPTURE_BASE was created because
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/// the functionality was moved from the PCH to the CPU.
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///
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EnableCStates (PmcGetAcpiBase () + PM_CST_LVL2);
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InitCstatePreWake ();
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}
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/**
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Disable/Enable the CState Pre-Wake Feature
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**/
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VOID
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InitCstatePreWake (
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VOID
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)
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{
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MSR_POWER_CTL_REGISTER PowerCtl;
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PowerCtl.Uint64 = AsmReadMsr64 (MSR_POWER_CTL);
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PowerCtl.Bits.CstatePrewakeDisable = 0;
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if (gCpuPowerMgmtTestConfig->CStatePreWake == FALSE) {
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PowerCtl.Bits.CstatePrewakeDisable = 1;
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}
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AsmWriteMsr64 (MSR_POWER_CTL, PowerCtl.Uint64);
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return;
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}
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/**
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Enables C-State support as specified by the input flags on all logical
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processors and sets associated timing requirements in the chipset.
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@param[in] C3IoAddress IO address to generate C3 states (PM base + 014 usually)
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**/
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VOID
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EnableCStates (
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IN UINT16 C3IoAddress
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)
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{
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MSR_POWER_CTL_REGISTER PowerCtl;
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MSR_C_STATE_LATENCY_CONTROL_0_REGISTER CStateLatencyControl0;
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MSR_C_STATE_LATENCY_CONTROL_1_REGISTER CStateLatencyControl1;
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MSR_C_STATE_LATENCY_CONTROL_2_REGISTER CStateLatencyControl2;
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MSR_C_STATE_LATENCY_CONTROL_3_REGISTER CStateLatencyControl3;
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MSR_C_STATE_LATENCY_CONTROL_4_REGISTER CStateLatencyControl4;
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MSR_C_STATE_LATENCY_CONTROL_5_REGISTER CStateLatencyControl5;
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UINT16 EnableCStateParameters;
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///
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/// Load the C-State parameters to pass to the core function.
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///
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EnableCStateParameters = C3IoAddress;
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///
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/// Enable C-States on all logical processors.
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///
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ApSafeEnableCStates(&EnableCStateParameters);
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mMpServices2Ppi->StartupAllAPs (
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mMpServices2Ppi,
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(EFI_AP_PROCEDURE) ApSafeEnableCStates,
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FALSE,
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0,
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(VOID *) &EnableCStateParameters
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);
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///
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/// If C-states are disabled or not supported, Disable C1e and retrun
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///
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if ((mPpmFlags & PPM_C_STATES) == 0) {
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PowerCtl.Uint64 = AsmReadMsr64 (MSR_POWER_CTL);
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PowerCtl.Bits.C1eEnable = 0;
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AsmWriteMsr64 (MSR_POWER_CTL, PowerCtl.Uint64);
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DEBUG ((DEBUG_INFO, "Setup C state disabled.Disable C1e. MSR(1FC) : 0x%08x\n", PowerCtl.Uint64));
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return;
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}
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///
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/// Configure supported enhanced C-states
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///
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/// Read Power Ctl MSR
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///
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PowerCtl.Uint64 = AsmReadMsr64 (MSR_POWER_CTL);
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DEBUG ((DEBUG_INFO, "MSR(1FC) before configuring C1E: 0x%08x\n", PowerCtl.Uint64));
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///
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/// Enable supported states
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///
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if (mPpmFlags & PPM_C1E) {
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PowerCtl.Bits.C1eEnable = 1;
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} else {
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PowerCtl.Bits.C1eEnable = 0;
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}
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///
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/// Update Power Control MSR
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///
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AsmWriteMsr64 (MSR_POWER_CTL, PowerCtl.Uint64);
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DEBUG ((DEBUG_INFO, "MSR(1FC) after configuring C1E: 0x%08x\n", PowerCtl.Uint64));
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///
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/// Program Interrupt response time limits used by processor to decided when to get into
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/// package C3
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///
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DEBUG ((DEBUG_INFO, "Programming the C3 (MSR 0x60A) Latencies \n"));
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//
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// Package C3 Interrupt response time
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//
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if (gCpuPowerMgmtTestConfig->CstateLatencyControl0Irtl > 0) {
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CStateLatencyControl0.Uint64 = AsmReadMsr64 (MSR_C_STATE_LATENCY_CONTROL_0);
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DEBUG ((DEBUG_INFO, "MSR(60A) before configuring Latency: 0x%08x\n", CStateLatencyControl0.Uint64));
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///
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/// Program Interrupt Response Time Unit and Latency for MSR 0x60A
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///
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CStateLatencyControl0.Bits.Value = gCpuPowerMgmtTestConfig->CstateLatencyControl0Irtl;
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CStateLatencyControl0.Bits.Multiplier = gCpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit;
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CStateLatencyControl0.Bits.Valid = 1;
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AsmWriteMsr64 (MSR_C_STATE_LATENCY_CONTROL_0, CStateLatencyControl0.Uint64);
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}
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///
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/// Program Interrupt response time limits used by processor to decided when to get into
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/// package C6 and C7
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///
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DEBUG ((DEBUG_INFO, "Programming the C6/C7/C8/C9/C10 (MSR 0x60B, 0x60C ,0x633, 0x634, 0x635 IRTL if not auto.\n"));
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//
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// Package C6/C7 short Interrupt response time
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//
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if (gCpuPowerMgmtTestConfig->CstateLatencyControl1Irtl > 0) {
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CStateLatencyControl1.Uint64 = AsmReadMsr64 (MSR_C_STATE_LATENCY_CONTROL_1);
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DEBUG ((DEBUG_INFO, "MSR(60B) before configuring Latency: 0x%08x\n", CStateLatencyControl1.Uint64));
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///
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/// Program Interrupt Response Time Unit and Latency for MSR 0x60B
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///
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CStateLatencyControl1.Bits.Value = gCpuPowerMgmtTestConfig->CstateLatencyControl1Irtl;
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CStateLatencyControl1.Bits.Multiplier = gCpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit;
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CStateLatencyControl1.Bits.Valid = 1;
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AsmWriteMsr64 (MSR_C_STATE_LATENCY_CONTROL_1, CStateLatencyControl1.Uint64);
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}
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//
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// Package C6/C7 long Interrupt response time
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//
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if (gCpuPowerMgmtTestConfig->CstateLatencyControl2Irtl > 0) {
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CStateLatencyControl2.Uint64 = AsmReadMsr64 (MSR_C_STATE_LATENCY_CONTROL_2);
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DEBUG ((DEBUG_INFO, "MSR(60C) before configuring Latency: 0x%08x\n", CStateLatencyControl2.Uint64));
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///
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/// Program Interrupt Response Time Unit and Latency for MSR 0x60C
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///
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CStateLatencyControl2.Bits.Value = gCpuPowerMgmtTestConfig->CstateLatencyControl2Irtl;
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CStateLatencyControl2.Bits.Multiplier = gCpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit;
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CStateLatencyControl2.Bits.Valid = 1;
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AsmWriteMsr64 (MSR_C_STATE_LATENCY_CONTROL_2, CStateLatencyControl2.Uint64);
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}
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//
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// Package C8 Interrupt response time
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//
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if (gCpuPowerMgmtTestConfig->CstateLatencyControl3Irtl > 0) {
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CStateLatencyControl3.Uint64 = AsmReadMsr64 (MSR_C_STATE_LATENCY_CONTROL_3);
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DEBUG ((DEBUG_INFO, "MSR(633) before configuring Latency: 0x%08x\n", CStateLatencyControl3.Uint64));
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///
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/// Program Interrupt Response Time Unit and Latency for MSR 0x633
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///
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CStateLatencyControl3.Bits.Value = gCpuPowerMgmtTestConfig->CstateLatencyControl3Irtl;
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CStateLatencyControl3.Bits.Multiplier = gCpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit;
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CStateLatencyControl3.Bits.Valid = 1;
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AsmWriteMsr64 (MSR_C_STATE_LATENCY_CONTROL_3, CStateLatencyControl3.Uint64);
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}
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//
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// Package C9 Interrupt response time
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//
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if (gCpuPowerMgmtTestConfig->CstateLatencyControl4Irtl > 0) {
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CStateLatencyControl4.Uint64 = AsmReadMsr64 (MSR_C_STATE_LATENCY_CONTROL_4);
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DEBUG ((DEBUG_INFO, "MSR(634) before configuring Latency: 0x%08x\n", CStateLatencyControl4.Uint64));
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///
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/// Program Interrupt Response Time Unit and Latency for MSR 0x634
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///
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CStateLatencyControl4.Bits.Value = gCpuPowerMgmtTestConfig->CstateLatencyControl4Irtl;
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CStateLatencyControl4.Bits.Multiplier = gCpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit;
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CStateLatencyControl4.Bits.Valid = 1;
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AsmWriteMsr64 (MSR_C_STATE_LATENCY_CONTROL_4, CStateLatencyControl4.Uint64);
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}
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///
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/// Package C10 Interrupt response time
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///
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if (gCpuPowerMgmtTestConfig->CstateLatencyControl5Irtl > 0) {
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CStateLatencyControl5.Uint64 = AsmReadMsr64 (MSR_C_STATE_LATENCY_CONTROL_5);
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DEBUG ((DEBUG_INFO, "MSR(635) before configuring Latency: 0x%08x\n", CStateLatencyControl5.Uint64));
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///
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/// Program Interrupt Response Time Unit and Latency for MSR 0x635
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///
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CStateLatencyControl5.Bits.Value = gCpuPowerMgmtTestConfig->CstateLatencyControl5Irtl;
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CStateLatencyControl5.Bits.Multiplier = gCpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit;
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CStateLatencyControl5.Bits.Valid = 1;
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AsmWriteMsr64 (MSR_C_STATE_LATENCY_CONTROL_5, CStateLatencyControl5.Uint64);
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}
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}
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/**
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Enable C-State support as specified by the input flags on a logical processor.
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Configure BIOS C1 Coordination (SMI coordination)
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Enable IO redirection coordination
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Choose proper coordination method
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Configure extended C-States
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This function must be MP safe.
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@param[in out] Buffer Pointer to a ENABLE_CSTATE_PARAMS containing the necessary
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information to enable C-States
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@retval EFI_SUCCESS Processor C-State support configured successfully.
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**/
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VOID
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EFIAPI
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ApSafeEnableCStates (
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IN OUT VOID *Buffer
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)
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{
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MSR_CLOCK_CST_CONFIG_CONTROL_REGISTER PmCfgCtrlMsr;
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MSR_PMG_IO_CAPTURE_BASE_REGISTER IoCaptAddr;
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MSR_IA32_MISC_ENABLE_REGISTER MiscEnable;
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UINT16 C3IoAddress;
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///
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/// Extract parameters from the buffer
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///
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C3IoAddress = *((UINT16 *) Buffer);
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///
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/// If C-states are disabled in setup, disable C-states
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///
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if (!(mPpmFlags & PPM_C_STATES)) {
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PmCfgCtrlMsr.Uint64 = AsmReadMsr64 (MSR_CLOCK_CST_CONFIG_CONTROL);
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PmCfgCtrlMsr.Bits.MaxPkgCState = 0;
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AsmWriteMsr64 (MSR_CLOCK_CST_CONFIG_CONTROL, PmCfgCtrlMsr.Uint64);
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return;
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}
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///
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/// Set C-state package limit to the highest C-state enabled
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///
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PmCfgCtrlMsr.Uint64 = AsmReadMsr64 (MSR_CLOCK_CST_CONFIG_CONTROL);
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///
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/// mPpmFlags might be override by others. So update the MaxPkgCState based on mPpmFlags setting.
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///
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if ((mPpmFlags & PPM_C10) && (PmCfgCtrlMsr.Bits.MaxPkgCState >= V_CSTATE_LIMIT_C10)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C10;
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} else if ((mPpmFlags & PPM_C9) && (PmCfgCtrlMsr.Bits.MaxPkgCState >= V_CSTATE_LIMIT_C9)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C9;
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} else if ((mPpmFlags & PPM_C8) && (PmCfgCtrlMsr.Bits.MaxPkgCState >= V_CSTATE_LIMIT_C8)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C8;
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} else if ((mPpmFlags & PPM_C7S) && (PmCfgCtrlMsr.Bits.MaxPkgCState >= V_CSTATE_LIMIT_C7S)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C7S;
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} else if ((mPpmFlags & PPM_C7) && (PmCfgCtrlMsr.Bits.MaxPkgCState >= V_CSTATE_LIMIT_C7)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C7;
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} else if ((mPpmFlags & PPM_C6) && (PmCfgCtrlMsr.Bits.MaxPkgCState >= V_CSTATE_LIMIT_C6)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C6;
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} else if ((mPpmFlags & PPM_C1) && (PmCfgCtrlMsr.Bits.MaxPkgCState >= V_CSTATE_LIMIT_C1)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C1;
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}
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if (gCpuPowerMgmtTestConfig->PkgCStateLimit != PkgCpuDefault) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = 0;
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if (gCpuPowerMgmtTestConfig->PkgCStateLimit < PkgCMax) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = gCpuPowerMgmtTestConfig->PkgCStateLimit;
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} else if ((mPpmFlags & PPM_C10) && (gCpuPowerMgmtTestConfig->PkgCStateLimit == PkgAuto)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C10;
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} else if ((mPpmFlags & PPM_C9) && (gCpuPowerMgmtTestConfig->PkgCStateLimit == PkgAuto)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C9;
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} else if ((mPpmFlags & PPM_C8) && (gCpuPowerMgmtTestConfig->PkgCStateLimit == PkgAuto)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C8;
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} else if ((mPpmFlags & PPM_C7S) && (gCpuPowerMgmtTestConfig->PkgCStateLimit == PkgAuto)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C7S;
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} else if ((mPpmFlags & PPM_C7) && (gCpuPowerMgmtTestConfig->PkgCStateLimit == PkgAuto)) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C7;
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} else if (mPpmFlags & PPM_C6) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C6;
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} else if (mPpmFlags & PPM_C1) {
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PmCfgCtrlMsr.Bits.MaxPkgCState = V_CSTATE_LIMIT_C1;
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}
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}
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///
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/// Configure C State IO redirection
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///
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if (gCpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection) {
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PmCfgCtrlMsr.Bits.IoMwaitRedirection = 1;
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}
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//
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// Enable TimedMwait
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//
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if (mPpmFlags & PPM_TIMED_MWAIT) {
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PmCfgCtrlMsr.Bits.TimedMwaitEnable = 1;
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}
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///
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/// Configure C-state auto-demotion
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///
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PmCfgCtrlMsr.Bits.C1StateAutoDemotionEnable = 0;
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if (gCpuPowerMgmtTestConfig->C1AutoDemotion) {
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///
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/// Enable C6/C7 Auto-demotion to C1
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///
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PmCfgCtrlMsr.Bits.C1StateAutoDemotionEnable = 1;
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}
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///
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/// Configure C-state un-demotion
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///
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PmCfgCtrlMsr.Bits.Enc1undemotion = 0;
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if (gCpuPowerMgmtTestConfig->C1UnDemotion) {
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///
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/// Enable un-demotion from demoted C1
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///
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PmCfgCtrlMsr.Bits.Enc1undemotion = 1;
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}
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///
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/// Configure Package C-state Demotion / un-demotion
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///
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PmCfgCtrlMsr.Bits.Enpkgcautodemotion = 0;
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PmCfgCtrlMsr.Bits.Enpkgcundemotion = 0;
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if (gCpuPowerMgmtTestConfig->PkgCStateDemotion) {
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///
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/// Enable Package C-state Demotion
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///
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PmCfgCtrlMsr.Bits.Enpkgcautodemotion = 1;
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}
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if (gCpuPowerMgmtTestConfig->PkgCStateUnDemotion) {
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///
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/// Enable Package C-state un-demotion
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///
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PmCfgCtrlMsr.Bits.Enpkgcundemotion = 1;
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}
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AsmWriteMsr64 (MSR_CLOCK_CST_CONFIG_CONTROL, PmCfgCtrlMsr.Uint64);
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///
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/// Enable MONITOR/MWAIT support
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/// (already done on BSP, but must be done on all components.)
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///
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MiscEnable.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
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MiscEnable.Bits.MONITOR = 1;
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AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnable.Uint64);
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///
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/// Configuration of I/O capture and I/O coordination SMI MSR.
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/// Configure the base port and range in the MSR to match LVL_X settings in ACPI tables
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/// Set I/O capture base port and range
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///
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IoCaptAddr.Uint64 = AsmReadMsr64 (MSR_PMG_IO_CAPTURE_BASE);
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///
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/// Mask off CST range and set the CST range
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///
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IoCaptAddr.Bits.CstRange = 0;
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if (mPpmFlags & PPM_C10) {
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IoCaptAddr.Bits.CstRange |= V_IO_CAPT_LVL7;
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} else if (mPpmFlags & PPM_C9) {
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IoCaptAddr.Bits.CstRange |= V_IO_CAPT_LVL6;
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} else if (mPpmFlags & PPM_C8) {
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IoCaptAddr.Bits.CstRange |= V_IO_CAPT_LVL5;
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} else if (mPpmFlags & PPM_C7) {
|
|
IoCaptAddr.Bits.CstRange |= V_IO_CAPT_LVL4;
|
|
} else if (mPpmFlags & PPM_C6) {
|
|
IoCaptAddr.Bits.CstRange |= V_IO_CAPT_LVL3;
|
|
}
|
|
///
|
|
/// Set the base CST address
|
|
///
|
|
IoCaptAddr.Bits.Lvl2b = C3IoAddress;
|
|
AsmWriteMsr64 (MSR_PMG_IO_CAPTURE_BASE, IoCaptAddr.Uint64);
|
|
return;
|
|
}
|
|
|