445 lines
14 KiB
C
445 lines
14 KiB
C
/** @file
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Header file for AlderLake PCH devices PCI Bus Device Function map.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2019 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PCH_BDF_ASSIGNMENT_H_
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#define _PCH_BDF_ASSIGNMENT_H_
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#define NOT_PRESENT 0xFF
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//
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// PCH PCIe Controllers
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//
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27
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#ifdef PCH_ADPP
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT
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#else
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 26
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 26
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 26
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 26
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#endif
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21 4
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22 5
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23 6
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#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24 7
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//
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// USB3 (XHCI) Controller PCI config
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//
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#define PCI_DEVICE_NUMBER_PCH_XHCI 20
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#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
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//
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// xDCI (OTG) USB Device Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_XDCI 20
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#define PCI_FUNCTION_NUMBER_PCH_XDCI 1
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//
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// Thermal Device
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//
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#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT
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//
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// CNVi WiFi
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//
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#define PCI_DEVICE_NUMBER_PCH_CNVI_WIFI 20
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#define PCI_FUNCTION_NUMBER_PCH_CNVI_WIFI 3
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//
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// South IEH Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_IEH 16
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#define PCI_FUNCTION_NUMBER_PCH_IEH 5
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//
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// CSME HECI #1
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI1 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI1 0
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//
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// CSME HECI #2
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI2 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI2 1
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//
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// CSME IDE-Redirection (IDE-R)
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//
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#define PCI_DEVICE_NUMBER_PCH_IDER 22
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#define PCI_FUNCTION_NUMBER_PCH_IDER 2
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//
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// CSME Keyboard and Text (KT) Redirection
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//
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#define PCI_DEVICE_NUMBER_PCH_KTR 22
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#define PCI_FUNCTION_NUMBER_PCH_KTR 3
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//
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// CSME HECI #3
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI3 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI3 4
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//
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// CSME HECI #4
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI4 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI4 5
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//
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// CSME MROM
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//
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#define PCI_DEVICE_NUMBER_PCH_MROM NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT
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//
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// CSME WLAN
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//
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#define PCI_DEVICE_NUMBER_PCH_WLAN 22
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#define PCI_FUNCTION_NUMBER_PCH_WLAN 7
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//
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// SATA Controllers
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//
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#define PCI_DEVICE_NUMBER_PCH_SATA_1 23
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#define PCI_FUNCTION_NUMBER_PCH_SATA_1 0
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#define PCI_DEVICE_NUMBER_PCH_SATA_2 NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_SATA_2 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_SATA_3 NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_SATA_3 NOT_PRESENT
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//
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// PCH LP & H Serial IO I2C #0 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0
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//
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// PCH LP & H Serial IO I2C #1 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1
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//
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// PCH LP & H Serial IO I2C #2 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2
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//
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// PCH LP & H Serial IO I2C #3 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3
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//
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// PCH LP & H Serial IO I2C #4 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 0
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//
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// PCH LP & H Serial IO I2C #5 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1
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//
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// PCH LP & H Serial IO I2C #6 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6 16
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6 0
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//
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// PCH LP & H Serial IO I2C #7 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7 16
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7 1
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//
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// Serial IO I3C #0 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I3C0 NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I3C0 NOT_PRESENT
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//
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// PCH LP, N & H Serial IO SPI #0 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2
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//
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// PCH LP, N & H Serial IO SPI #1 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3
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//
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// PCH LP, N & H Serial IO SPI #2 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2 18
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2 6
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//
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// PCH LP, N & H Serial IO SPI #3 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3 0
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//
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// PCH LP, N & H Serial IO SPI #4 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4 1
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//
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// PCH LP, N & H Serial IO SPI #5 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5 2
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#define PCI_DEVICE_NUMBER_PCH_H_SERIAL_IO_SPI5 17
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#define PCI_FUNCTION_NUMBER_PCH_H_SERIAL_IO_SPI5 4
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//
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// PCH LP, N & H Serial IO SPI #6 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6 3
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#define PCI_DEVICE_NUMBER_PCH_H_SERIAL_IO_SPI6 17
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#define PCI_FUNCTION_NUMBER_PCH_H_SERIAL_IO_SPI6 5
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//
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// PCH LP, N & H Serial IO UART #0 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0
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//
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// PCH LP, N & H Serial IO UART #1 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1
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//
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// PCH LP, N & H Serial IO UART #2 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 2
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//
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// PCH LP, N & H Serial IO UART #3 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3 0
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//
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// PCH LP, N & H Serial IO UART #4 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4 1
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//
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// PCH LP, N & H Serial IO UART #5 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5 2
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//
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// PCH LP, N & H Serial IO UART #6 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6 3
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//
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// DMA-SMBus Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_DMA_SMBUS 30
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#define PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS 4
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//
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// TSN GbE Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_TSN 30
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#define PCI_FUNCTION_NUMBER_PCH_TSN 4
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//
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// LPC Controller (D31:F0)
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//
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#define PCI_DEVICE_NUMBER_PCH_LPC 31
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#define PCI_FUNCTION_NUMBER_PCH_LPC 0
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//
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// eSPI Controller (D31:F0)
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//
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#define PCI_DEVICE_NUMBER_PCH_ESPI 31
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#define PCI_FUNCTION_NUMBER_PCH_ESPI 0
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//
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// Primary to Sideband (P2SB) Bridge (D31:F1)
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//
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#define PCI_DEVICE_NUMBER_PCH_P2SB 31
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#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
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//
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// PMC (D31:F2)
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//
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#define PCI_DEVICE_NUMBER_PCH_PMC 31
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#define PCI_FUNCTION_NUMBER_PCH_PMC 2
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//
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// PMC SSRAM Registers (D20:F2)
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//
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#define PCI_DEVICE_NUMBER_PCH_PMC_SSRAM 20
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#define PCI_FUNCTION_NUMBER_PCH_PMC_SSRAM 2
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//
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// HD-A Controller (D31:F3)
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//
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#define PCI_DEVICE_NUMBER_PCH_HDA 31
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#define PCI_FUNCTION_NUMBER_PCH_HDA 3
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//
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// SMBus Controller (D31:F4)
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//
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#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
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#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4
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//
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// SPI Controller (D31:F5)
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//
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#define PCI_DEVICE_NUMBER_PCH_SPI 31
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#define PCI_FUNCTION_NUMBER_PCH_SPI 5
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//
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// Gigabit Ethernet LAN Controller (D31:F6)
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//
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#define PCI_DEVICE_NUMBER_GBE 31
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#define PCI_FUNCTION_NUMBER_GBE 6
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//
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// PCH TraceHub (D31:F7)
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//
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#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31
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#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7
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//
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// ISH Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_ISH 18
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#define PCI_FUNCTION_NUMBER_PCH_ISH 0
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//
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// SCS SDCARD Controller PCI config (not present in ADL)
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//
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#define PCI_DEVICE_NUMBER_PCH_SCS_SDCARD NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_SCS_SDCARD NOT_PRESENT
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//
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// SCS eMMC Controller PCI config
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//
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#define PCI_DEVICE_NUMBER_PCH_SCS_EMMC 26
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#define PCI_FUNCTION_NUMBER_PCH_SCS_EMMC 0
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//
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// SCS UFS Controller PCI config
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//
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#define PCI_DEVICE_NUMBER_PCH_SCS_UFS0 18
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#define PCI_FUNCTION_NUMBER_PCH_SCS_UFS0 5
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#define PCI_DEVICE_NUMBER_PCH_SCS_UFS1 18
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#define PCI_FUNCTION_NUMBER_PCH_SCS_UFS1 7
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//
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// THC#0 Controller ID1,ID2 PCI config
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//
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#define PCI_DEVICE_NUMBER_PCH_THC0 16
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#define PCI_FUNCTION_NUMBER_PCH_THC0 6
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//
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// THC#1 Controller ID1,ID2 PCI config
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//
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#define PCI_DEVICE_NUMBER_PCH_THC1 16
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#define PCI_FUNCTION_NUMBER_PCH_THC1 7
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#endif // _PCH_BDF_ASSIGNMENT_H_
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