124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
/** @file
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Build time limits of PCH resources.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2013 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PCH_LIMITS_H_
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#define _PCH_LIMITS_H_
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/*
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* Defines povided in this file are indended to be used only where static value
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* is needed. They are set to values which allow to accomodate multiple projects
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* needs. Where runtime usage is possible please used dedicated functions from
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* PchInfoLib to retrieve accurate values
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*/
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//
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// HSIO limits
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//
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#define PCH_MAX_HSIO_LANES 38
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//
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// PCIe limits
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//
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#define PCH_MAX_PCIE_ROOT_PORTS 28
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#define PCH_MAX_PCIE_CONTROLLERS 7
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//
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// PCIe clocks limits
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//
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#define PCH_MAX_PCIE_CLOCKS 18
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//
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// DMI lanes
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//
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#define PCH_MAX_DMI_LANES 8
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//
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// PCH PSF segments
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//
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#define PCH_MAX_PSF_SEGMENTS 8
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//
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// RST PCIe Storage Cycle Router limits
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//
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#define PCH_MAX_RST_PCIE_STORAGE_CR 3
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//
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// SATA limits
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//
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#define PCH_MAX_SATA_CONTROLLERS 3
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#define PCH_MAX_SATA_PORTS 8
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//
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// SerialIo limits
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//
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#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8
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#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7
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#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2
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#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7
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#define PCH_MAX_SERIALIO_I3C_CONTROLLERS 1
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//
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// THC limits
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//
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#define PCH_MAX_THC_CONTROLLERS 2
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//
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// ISH limits
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//
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#define PCH_MAX_ISH_GP_PINS 8
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#define PCH_MAX_ISH_UART_CONTROLLERS 2
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#define PCH_MAX_ISH_I2C_CONTROLLERS 3
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#define PCH_MAX_ISH_SPI_CONTROLLERS 1
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#define PCH_MAX_ISH_SPI_CS_PINS 1
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//
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// HDA limits
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//
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#define PCH_MAX_HDA_SDI 2
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#define PCH_MAX_HDA_SSP_LINK_NUM 6
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#define PCH_MAX_HDA_DMIC_LINK_NUM 2
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#define PCH_MAX_HDA_SNDW_LINK_NUM 4
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//
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// Number of eSPI slaves
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//
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#define PCH_MAX_ESPI_SLAVES 2
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//
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// Number of UFS controllers
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//
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#define PCH_MAX_UFS_DEV_NUM 2
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#define SETUP_MAX_USB2_PORTS 16
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#define SETUP_MAX_USB3_PORTS 10
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#define PCH_MAX_ADR_SOURCE_NUMBER 25
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#endif // _PCH_LIMITS_H_
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