76 lines
2.9 KiB
C
76 lines
2.9 KiB
C
/** @file
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This file contains routines that get PCI Express Address through I/O Ports CF8 and CFC
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2017 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Library/BaseLib.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#define PCIEX_BAR_REG 0x80000060 // B0:D0:F0:R60
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#define PCIEX_BAR_EN_MASK 0x1
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#define PCIEX_BAR_LENGTH_MASK 0x6
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#define PCIEX_BAR_ADDR_MASK 0x7FFC000000
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/**
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This procedure will get PCIE address
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@param[in] Bus Pci Bus Number
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@param[in] Device Pci Device Number
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@param[in] Function Pci Function Number
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@retval PCIE address
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**/
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UINTN
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MmPciBase (
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IN UINT32 Bus,
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IN UINT32 Device,
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IN UINT32 Function
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)
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{
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UINT64 PciExpressBaseValue = 0;
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BOOLEAN InterruptState;
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ASSERT ((Bus <= 0xFF) && (Device <= 0x1F) && (Function <= 0x7));
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//
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// Get PciExpressBaseAddress from PCIEX_BAR_REG (B0:D0:F0:R60)
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//
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InterruptState = SaveAndDisableInterrupts ();
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IoWrite32(0xCF8, PCIEX_BAR_REG);
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PciExpressBaseValue = IoRead32(0xCFC);
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SetInterruptState (InterruptState);
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ASSERT ((PciExpressBaseValue & PCIEX_BAR_EN_MASK) == 1);
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return ((UINTN) (PciExpressBaseValue & PCIEX_BAR_ADDR_MASK) + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12));
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}
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