502 lines
14 KiB
C
502 lines
14 KiB
C
/** @file
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BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2014 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _BUP_MSGS_H
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#define _BUP_MSGS_H
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#include <MeBiosPayloadData.h>
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#pragma pack(1)
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///
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/// BUP group IDs
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///
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#define BUP_COMMON_GROUP_ID 0xF0
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#define BUP_ICC_GROUP_ID 0xF1
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#define BUP_MPHY_GROUP_ID 0xF2
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#define BUP_PM_GROUP_ID 0xF3
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///
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/// Defines for Command
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///
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///
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/// Defines for BUP_COMMON_GROUP_ID Command
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///
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#define DRAM_INIT_DONE_CMD 0x01
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#define MBP_REQUEST_CMD 0x02
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#define ME_ENABLE_CMD 0x03
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#define HMRFPO_DISABLE_CMD 0x04
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#define TERMINATE_HECI_CMD 0x05
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#define GET_IMR_SIZE_CMD 0x0C
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#define MANUF_RESET_AND_HALT_CMD 0x0E
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#define BUP_GET_ME_TYPE 0x11
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#define GET_ER_LOG_CMD 0x1B
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#define SET_EDEBUG_STATE_CMD 0x1E
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#define DATA_CLEAR_CMD 0x20
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#define GET_IP_FIRMWARE_CMD 0x21
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#define GET_DEBUG_TOKEN_DATA_CMD 0x22
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#define GET_BIOS_SEED_CMD 0x23
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///
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/// Defines for BUP_MPHY_GROUP_ID Command
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///
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#define ICC_CMD 0x01
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///
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/// Defines for BUP_MPHY_GROUP_ID Command
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///
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#define MPHY_READ_FROM_MPHY_CMD 0x2
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///
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/// Defines for BUP_PM_GROUP_ID Command
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///
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#define NPCR_NOTIFICATION_CMD 0x1
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///
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/// Common group definitions
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///
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///
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/// DRAM Init Done definitions
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///
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///
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/// Memory Init Status codes
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///
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#define BIOS_MSG_DID_SUCCESS 0
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#define BIOS_MSG_DID_NO_MEMORY 0x1
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#define BIOS_MSG_DID_INIT_ERROR 0x2
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typedef struct {
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UINT32 BiosImrsBaLow;
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UINT32 BiosImrsBaHigh;
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} DRAM_INIT_DONE_IMRS_REQ_DATA;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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DRAM_INIT_DONE_IMRS_REQ_DATA ImrData;
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UINT32 Flags;
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UINT8 Reserved1[2];
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UINT8 MemStatus;
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UINT8 Reserved2;
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} DRAM_INIT_DONE_CMD_REQ;
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//
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// Response Flags Definitions
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//
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#define ME_OPTIMIZED_BOOT_FLAG BIT1
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///
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/// BIOS Reset Action Codes
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///
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#define DID_ACK_NON_PCR 0x1
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#define DID_ACK_PCR 0x2
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#define DID_ACK_GRST 0x3
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typedef struct {
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UINT32 AdrLow;
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UINT32 AdrHigh;
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} PCI_2_PRIV_BASE;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 Reserved1[4];
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PCI_2_PRIV_BASE Pci2PrivBase;
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UINT8 Flags;
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UINT8 BiosAction;
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UINT8 Reserved2[6];
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} DRAM_INIT_DONE_CMD_RESP;
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typedef union {
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DRAM_INIT_DONE_CMD_REQ Request;
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DRAM_INIT_DONE_CMD_RESP Response;
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} DRAM_INIT_DONE_CMD_BUFFER;
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#define MAX_MBP_ITEMS_SIZE 125 * sizeof (UINT32)
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 SkipMbp;
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} GET_MBP_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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MBP_HEADER MbpHeader;
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UINT32 MbpItems[MAX_MBP_ITEMS_SIZE];
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} GET_MBP_RESP;
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typedef union {
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GET_MBP_REQ Request;
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GET_MBP_RESP Response;
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} GET_MBP_BUFFER;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} ME_ENABLE_CMD_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} ME_ENABLE_CMD_RESP;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} HMRFPO_DISABLE_CMD_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} HMRFPO_DISABLE_CMD_RESP;
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typedef union {
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HMRFPO_DISABLE_CMD_REQ Request;
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HMRFPO_DISABLE_CMD_RESP Response;
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} HMRFPO_DISABLE_CMD_BUFFER;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 Reserved;
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} TERMINATE_HECI_CMD_REQ;
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///
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/// Get IMR size message
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///
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typedef struct {
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UINT32 BiosImrDisableMask0;
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UINT32 BiosImrDisableMask1;
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UINT32 Pci2PrivSize;
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} GET_IMR_CMD_REQ_DATA;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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GET_IMR_CMD_REQ_DATA Data;
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} GET_IMR_CMD_REQ;
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typedef struct {
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UINT32 ImrsSize;
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UINT32 Alignment;
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UINT32 Flags;
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} GET_IMR_CMD_RESP_DATA;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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GET_IMR_CMD_RESP_DATA Data;
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} GET_IMR_CMD_RESP;
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typedef union {
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GET_IMR_CMD_REQ Request;
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GET_IMR_CMD_RESP Response;
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} GET_IMR_CMD_BUFFER;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} MANUF_RESET_AND_HALT_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} MANUF_RESET_AND_HALT_RESP;
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typedef union {
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MANUF_RESET_AND_HALT_REQ Request;
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MANUF_RESET_AND_HALT_RESP Response;
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} MANUF_RESET_AND_HALT_BUFFER;
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typedef struct {
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UINT32 FwType : 3;
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UINT32 FwSubType : 8;
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UINT32 Reserved : 21;
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} FW_TYPE_DATA;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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FW_TYPE_DATA FwTypeData;
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} GEN_GET_FW_TYPE_ACK;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} GEN_GET_FW_TYPE;
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typedef union {
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GEN_GET_FW_TYPE Request;
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GEN_GET_FW_TYPE_ACK Response;
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} GEN_GET_FW_TYPE_BUFFER;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT8 FirstLogEntryIndex;
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UINT16 Flags;
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UINT8 Reserved;
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} GET_ER_LOG_CMD_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT8 MeasuredBootEnabled;
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UINT8 FirstLogEntryIndex;
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UINT8 LastLogEntryIndex;
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UINT8 RemainingEntries;
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UINT16 DataLength;
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UINT8 LogData[]; // Data buffer
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} GET_ER_LOG_CMD_RESP;
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typedef union {
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GET_ER_LOG_CMD_REQ Request;
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GET_ER_LOG_CMD_RESP Response;
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} GET_ER_LOG_BUFFER;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 State;
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} SET_EDEBUG_MODE_STATE_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} SET_EDEBUG_MODE_STATE_RESP;
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typedef union {
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SET_EDEBUG_MODE_STATE_REQ Request;
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SET_EDEBUG_MODE_STATE_RESP Response;
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} SET_EDEBUG_MODE_STATE_BUFFER;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 Reserved;
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} DATA_CLEAR_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} DATA_CLEAR_RESP;
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typedef union {
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DATA_CLEAR_REQ Request;
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DATA_CLEAR_RESP Response;
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} DATA_CLEAR_BUFFER;
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#define MAX_DIGEST_SIZE 64
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#define IP_LOADING_CMD_VERSION 1
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 Version;
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UINT32 Operation;
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UINT32 DramBaseLow;
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UINT32 DramBaseHigh;
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UINT32 MemorySize;
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UINT32 Reserved;
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} IP_LOADING_CMD_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 PayloadSize;
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UINT32 Reserved[2];
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UINT32 Status;
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UINT8 HashType;
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UINT8 Hash[];
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} IP_LOADING_CMD_RESP;
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typedef union {
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IP_LOADING_CMD_REQ Request;
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IP_LOADING_CMD_RESP Response;
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} IP_LOADING_CMD_BUFFER;
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/**
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Enable Debug Transports specifying Power Controls.
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0000: Use existing setup settings</b>
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0001: Enable DCI.OOB + DCI.DBC w/ power overrides.
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0010: Enable DCI.OOB-2 w/o power overrides.
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0011: Disable Debug.
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Everything else is reserved.
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**/
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typedef enum {
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SetupMenuDefault = 0x0,
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EnabledAll = 0x1,
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EnabledLowPower = 0x2,
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ForceDisabled = 0x3
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} STREAMING_TRACE_SINK;
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typedef union {
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struct {
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UINT32 ExposeDebugMenu : 1; ///< Expose Debug Menu. 0: Debug menu is hidden; 1: Expose debug menu if hidden
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/**
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Refer to definition of STREAMING_TRACE_SINK
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**/
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UINT32 StreamingTraceSink : 4;
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/**
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Force TraceHub "on" unconditionally.
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0: Normal. BIOS shall enable or disable TraceHub according to the value of BIT24 in scratchpad 0 register or BIOS menu configuration
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1: Force on. BIOS shall keep TraceHub enabled unconditionally
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**/
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UINT32 TraceHubForceOn : 1;
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UINT32 TraceEnable : 1; ///< Enable BIOS traces. 0: Normal behavior; 1: Enable Trace Messaging
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UINT32 JtagC10PgDis : 1; ///< Disable JTAG C10 power gate 0: Normal behavior (Follow BIOS menu configuration); 1: Disable JTAG C10 power gate
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UINT32 UsbOverCurrentOvrd : 1; ///< Enable USB overcurrent override. 0: Normal behavior (Follow BIOS menu configuration); 1: Enable USB overcurrent override
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UINT32 IntelReserved : 7; ///< Reserved for future Intel use
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UINT32 OemReserved : 16; ///< Reserved for OEM use
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} Fields;
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UINT32 Data;
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} DEBUG_TOKEN_KNOB_DATA;
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#define BOOTLOADER_SEED_LEN_EX 64
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#define BIOS_ADDITIONAL_DATA_LEN 48
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typedef struct {
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UINT32 SeedDebugProperty : 1;
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UINT32 SeedHwFpfProperty : 1;
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UINT32 SeedBtgProperty : 1;
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UINT32 SeedType : 3;
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UINT32 SeedLength : 2;
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UINT32 Reserved : 24;
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} SEED_PROPERTIES_BIT_MAP;
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typedef struct {
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UINT32 IsIntelUnlocked : 1;
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UINT32 IsOemUnlocked : 1;
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UINT32 IsDamEnabled : 1;
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UINT32 IsHwFpfEnabled : 1;
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UINT32 IsBtgEnabled : 1;
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UINT32 Reserved : 27;
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} SEED_INFO_BIT_MAP;
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typedef struct {
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UINT8 CsmeSvn;
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UINT8 BiosSvn;
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SEED_INFO_BIT_MAP SeedInfoBitMap;
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} SEED_INFO;
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typedef struct {
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UINT8 CsmeSvn;
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UINT8 BiosSvn;
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SEED_PROPERTIES_BIT_MAP SeedPropertiesBitMap;
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UINT8 BiosAdditionalData[BIOS_ADDITIONAL_DATA_LEN];
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} SEED_PROPERTIES;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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SEED_PROPERTIES BiosSeedProperties;
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UINT8 LockSeedGeneration;
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} GET_BIOS_SEED_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 EphemeralKeyCounter;
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SEED_INFO BiosSeedInfo;
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UINT8 BiosSeed[BOOTLOADER_SEED_LEN_EX];
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} GET_BIOS_SEED_RESP;
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typedef union {
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GET_BIOS_SEED_REQ Request;
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GET_BIOS_SEED_RESP Response;
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} GET_BIOS_SEED_BUFFER;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} GET_DEBUG_TOKEN_DATA_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT8 TokenId; ///< 1: Intel Token. 2: OEM Token
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UINT8 Reserved[3];
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DEBUG_TOKEN_KNOB_DATA KnobData;
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} GET_DEBUG_TOKEN_DATA_RESP;
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typedef union {
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GET_DEBUG_TOKEN_DATA_REQ Request;
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GET_DEBUG_TOKEN_DATA_RESP Response;
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} GET_DEBUG_TOKEN_DATA_BUFFER;
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///
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/// ICC group defines
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///
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typedef struct {
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UINT32 FwNeedsWarmResetFlag:1; ///< BIT0
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UINT32 Reserved:31; ///< BIT1-31
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} ICC_MESSAGE_RESP_DATA;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} ICC_CMD_REQ;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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ICC_MESSAGE_RESP_DATA Data;
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} ICC_CMD_RESP;
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typedef union {
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ICC_CMD_REQ Request;
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ICC_CMD_RESP Response;
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} ICC_CMD_BUFFER;
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///
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/// MPHY group defines
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///
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typedef struct{
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 Reserved1;
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UINT32 Offset;
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UINT32 Reserved2;
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UINT32 NumOfBytes;
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} BUP_MPHY_READ_FROM_MPHY;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT32 Reserved1;
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UINT32 FileSize;
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UINT32 Reserved2;
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UINT32 ReadSize;
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UINT32 Reserved3;
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UINT8 Data[];
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} BUP_MPHY_READ_FROM_MPHY_ACK;
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typedef union {
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BUP_MPHY_READ_FROM_MPHY Request;
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BUP_MPHY_READ_FROM_MPHY_ACK Response;
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} BUP_MPHY_READ_FROM_MPHY_BUFFER;
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///
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/// PM group defines
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///
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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} HR_NOTIFICATION_CMD;
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typedef struct {
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MKHI_MESSAGE_HEADER MkhiHeader;
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UINT8 ResetRequested;
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} HR_NOTIFICATION_CMD_RESP;
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typedef union {
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HR_NOTIFICATION_CMD Request;
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HR_NOTIFICATION_CMD_RESP Response;
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} HR_NOTIFICATION_BUFFER;
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#pragma pack()
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#endif // _BUP_MSGS_H
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