114 lines
4.1 KiB
C
114 lines
4.1 KiB
C
/** @file
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CNVi policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CNVI_CONFIG_H_
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#define _CNVI_CONFIG_H_
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#define CNVI_CONFIG_REVISION 4
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extern EFI_GUID gCnviConfigGuid;
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#define CNVI_PREMEM_CONFIG_REVISION 1
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extern EFI_GUID gCnviPreMemConfigGuid;
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#pragma pack (push,1)
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/**
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CNVi Mode options
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**/
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typedef enum {
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CnviModeDisabled = 0,
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CnviModeAuto
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} CNVI_MODE;
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/**
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CNVi signals pin muxing settings. If signal can be enable only on a single pin
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then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in GpioPins*.h
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for supported settings on a given platform
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**/
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typedef struct {
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UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*
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UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*
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} CNVI_PIN_MUX;
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/**
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The CNVI_CONFIG block describes the expected configuration of the CNVi IP.
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<b>Revision 1</b>: - Initial version.
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<b>Revision 2</b>: - Add DdrRfim.
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<b>Revision 3</b>: - Add WifiCore.
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<b>Revision 4</b>: - Move DdrRfim to Pre-Mem config.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This option allows for automatic detection of Connectivity Solution.
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Auto Detection assumes that CNVi will be enabled when available;
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Disable allows for disabling CNVi.
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CnviModeDisabled = Disabled,
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<b>CnviModeAuto = Auto Detection</b>
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**/
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UINT32 Mode : 1;
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UINT32 BtCore : 1; ///< The option to turn ON or OFF the BT Core. 0: Disabled, <b>1: Enabled</b>
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/**
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The option to enable or disable BT Audio Offload.
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<b>0: Disabled</b>, 1: Enabled
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@note This feature only support with Intel(R) Wireless-AX 22560
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**/
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UINT32 BtAudioOffload : 1;
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UINT32 WifiCore : 1; ///< The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, <b>1: Enabled</b>
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UINT32 RsvdBits : 28;
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/**
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CNVi PinMux Configuration
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RESET#/CLKREQ to CRF, can have two alternative mappings, depending on board routing requirements.
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**/
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CNVI_PIN_MUX PinMux;
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} CNVI_CONFIG;
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/**
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The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.
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<b>Revision 1</b>: - Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT8 DdrRfim; ///< The option to enable or disable DDR RFI Mitigation. 0: Disabled, <b>1: Enabled</b>
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UINT8 RsvdByte[3];
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} CNVI_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _CNVI_CONFIG_H_
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