129 lines
5.9 KiB
C
129 lines
5.9 KiB
C
/** @file
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Functional Safety policy.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2019-2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _FUSA_CONFIG_H_
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#define _FUSA_CONFIG_H_
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/**
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Making any setup structure change after code frozen
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will need to maintain backward compatibility, bump up
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structure revision and update below history table\n
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<b>Revision 1</b>: - Initial version.
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<b>Revision 3</b>: - Add FusaConfigEnable switch, BIST scan and locksteps for module.
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**/
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#define FUSA_CONFIG_REVISION 3
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extern EFI_GUID gFusaConfigGuid;
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#pragma pack (push,1)
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/**
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The FUSA_CONFIG block describes the expected configuration of Functional Safety
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Enable/Disable Fusa feature on Display
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Fusa configuration on Display <b>0: Disable</b>; 1: Enable.
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Enable/Disable Fusa feature on IOP MCA Check
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Fusa configuration on IOP MCA Check <b>0: Disable</b>; 1: Enable.
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**/
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UINT32 DisplayFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on DE: 0=Disable, 1=Enable
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UINT32 GraphicFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on GT: 0=Disable, 1=Enable
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UINT32 OpioFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on OPIO: 0=Disable, 1=Enable
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UINT32 PsfFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on PSF: 0=Disable, 1=Enable
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UINT32 IopFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on IOP: 0=Disable, 1=Enable
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UINT32 IopFusaMcaCheckEnable : 1; ///< Enable/Disable FuSa feature on IOP MCA Check Enable: 0=Disable, 1=Enable
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UINT32 FusaConfigEnable : 1; ///< Enable/Disable FuSa feature: 0=Disable, 1=Enable
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UINT32 FusaRunStartupArrayBist : 1; ///< Enabling this will execute startup array test during boot
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UINT32 FusaRunStartupScanBist : 1; ///< Enabling this will execute startup scan test during boot
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UINT32 FusaRunPeriodicScanBist : 1; ///< Enabling this will execute periodic scan test during boot
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UINT32 Module0Lockstep : 2; ///< Enable/Disable Lockstep for Atom module 1, which has 4 cores;
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///< 0: Disable lockstep; 1: Enable lockstep for Core 0 with Core 1, Core 2 with Core 3;
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///< 2: Enable lockstep for Core 0 with Core 1; 3: Enable lockstep for Core 2 with Core 3
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UINT32 Module1Lockstep : 2; ///< Enable/Disable Lockstep for Atom module 1, which has 4 cores;
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///< 0: Disable lockstep; 1: Enable lockstep for Core 0 with Core 1, Core 2 with Core 3;
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///< 2: Enable lockstep for Core 0 with Core 1; 3: Enable lockstep for Core 2 with Core 3
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UINT32 RsvdBits0 : 18; ///< Reserved bits
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} FUSA_CONFIG;
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#pragma pack (pop)
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/**
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**/
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#define MSR_FUSA_CONFIG 0x000002D1
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#define MSR_TRIGGER_STARTUP_MEM_BIST 0x000002D4
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#define MSR_STARTUP_MEM_BIST_STATUS 0x000002D5
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#define MSR_FUSA_CAPABILITIES_A 0x000002D9
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#define B_MSR_FUSA_CAP_STARTUP_SCAN_DIAGNOGSIS_MASK BIT0
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#define B_MSR_FUSA_CAP_STARTUP_ARRAY_DIAGNOGSIS_MASK BIT1
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#define B_MSR_FUSA_CAP_PERIODIC_ARRAY_DIAGNOGSIS_MASK BIT2
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#define B_MSR_FUSA_CAP_LOCKSTEP_MODE_MASK BIT3
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#define B_MSR_FUSA_CAP_PERIODIC_SCAN_DIAGNOGSIS_MASK BIT4
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#define MAX_AP_COUNT 24
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typedef union {
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BOOLEAN GlobalApEnable;
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UINT8 CurrProcessor;
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BOOLEAN LockStepEn[MAX_AP_COUNT];
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} LOCKSTEP_CONFIG;
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/**
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LOCKSTEP ENABLE
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**/
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#define MSR_ENABLE_LSM 0x000002D8
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typedef enum {
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LockstepDisabled = 0x0,
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LockstepC0C1_C2C3 = 0x1,
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LockstepC0C1 = 0x2,
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LockstepC2C3 = 0x3
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} LOCKSTEP_MODE;
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#define GRT_MOD8_LPID0_APIC_ID 0x40
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#define GRT_MOD8_LPID1_APIC_ID 0x42
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#define GRT_MOD8_LPID2_APIC_ID 0x44
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#define GRT_MOD8_LPID3_APIC_ID 0x46
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#define GRT_MOD9_LPID0_APIC_ID 0x48
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#define GRT_MOD9_LPID1_APIC_ID 0x4A
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#define GRT_MOD9_LPID2_APIC_ID 0x4C
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#define GRT_MOD9_LPID3_APIC_ID 0x4E
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#endif // _FUSA_CONFIG_H_
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