89 lines
4.1 KiB
C
89 lines
4.1 KiB
C
/** @file
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IoApic policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _IOAPIC_CONFIG_H_
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#define _IOAPIC_CONFIG_H_
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#define PCH_IOAPIC_CONFIG_REVISION 1
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extern EFI_GUID gIoApicConfigGuid;
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#pragma pack (push,1)
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/**
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The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH
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IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
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not TRUE. Bus:device:function fields will be programmed to the register
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P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
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As the Requester ID when initiating Interrupt Messages to the processor.
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As the Completer ID when responding to the reads targeting the IOxAPI's
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Memory-Mapped I/O registers.
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This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
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program this field to provide a unique Bus:Device:Function number for the
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internal IOxAPIC.
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The address resource range of IOAPIC must be reserved in E820 and ACPI as
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system resource.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119
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/**
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Enable 8254 Static Clock Gating during early POST time. 0: Disable, <b>1: Enable</b>
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Setting 8254CGE is required to support SLP_S0.
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Enable this if 8254 timer is not used.
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However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer.
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Make sure it is disabled to support legacy OS using 8254 timer.
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@note:
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For some OS environment that it needs to set 8254CGE in late state it should
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set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in SMM later.
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This is also required during S3 resume.
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To avoid SMI requirement in S3 reusme path, it can enable the Enable8254ClockGatingOnS3
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and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_SAI.
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**/
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UINT32 Enable8254ClockGating : 1;
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/**
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Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, <b>1: Enable</b>
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This is only applicable when Enable8254ClockGating is disabled.
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If Enable8254ClockGating is enabled, RC will do the 8254 CGE programming on
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S3 resume path as well.
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**/
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UINT32 Enable8254ClockGatingOnS3 : 1;
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UINT32 RsvdBits1 : 29; ///< Reserved bits
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UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is <b>0x02</b>.
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UINT8 Rsvd0[3]; ///< Reserved bytes
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} PCH_IOAPIC_CONFIG;
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#pragma pack (pop)
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#endif // _IOAPIC_CONFIG_H_
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