84 lines
3.5 KiB
C
84 lines
3.5 KiB
C
/** @file
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FlashProtection policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _FLASH_PROTECTION_CONFIG_H_
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#define _FLASH_PROTECTION_CONFIG_H_
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#define PCH_FLASH_PROTECTION_CONFIG_REVISION 1
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extern EFI_GUID gFlashProtectionConfigGuid;
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#pragma pack (push,1)
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//
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// Flash Protection Range Register
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//
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#define PCH_FLASH_PROTECTED_RANGES 5
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/**
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Protected Flash Range
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**/
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typedef struct {
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UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
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UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits : 30; ///< Reserved
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/**
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The address of the upper limit of protection
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This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
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**/
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UINT16 ProtectedRangeLimit;
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/**
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The address of the upper limit of protection
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This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
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**/
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UINT16 ProtectedRangeBase;
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} PROTECTED_RANGE;
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/**
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The PCH provides a method for blocking writes and reads to specific ranges
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in the SPI flash when the Protected Ranges are enabled.
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PROTECTED_RANGE is used to specify if flash protection are enabled,
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the write protection enable bit and the read protection enable bit,
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and to specify the upper limit and lower base for each register
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Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
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and set the limit and base accordingly.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
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} PCH_FLASH_PROTECTION_CONFIG;
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#pragma pack (pop)
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#endif // _FLASH_PROTECTION_CONFIG_H_
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