90 lines
3.0 KiB
C
90 lines
3.0 KiB
C
/** @file
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This file contains information about Hybrid Graphics.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _HG_INFO_HOB_H_
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#define _HG_INFO_HOB_H_
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#include "HybridGraphicsInfo.h"
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extern EFI_GUID gHybridGraphicsInfoHobGuid;
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#pragma pack (1)
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///
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/// SA GPIO Data Structure
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///
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typedef struct {
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UINT8 ExpanderNo; ///< =Expander No For I2C based GPIO
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UINT32 GpioNo; ///< GPIO pad
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BOOLEAN Active; ///< 0=Active Low; 1=Active High
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} PCIE_GPIO;
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///
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/// SA PCIE RTD3 GPIO Data Structure
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///
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typedef struct {
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UINT8 GpioSupport; ///< 0=Not Supported; 1=PCH based; 2=I2C Based
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PCIE_GPIO HoldRst; ///< Offset 8 This field contain PCIe HLD RESET GPIO value and level information
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PCIE_GPIO PwrEnable; ///< This field contain PCIe PWR Enable GPIO value and level information
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UINT32 WakeGpioNo; ///< This field contain PCIe RTD3 Device Wake GPIO number
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} PCIE_RTD3_GPIO;
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///
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/// HG Info HOB
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///
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typedef struct {
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HG_MODE HgMode;
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UINT8 RootPortIndex;
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PCIE_RTD3_GPIO Rtd3Pcie0Gpio;
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PCIE_RTD3_GPIO Rtd3Pcie1Gpio;
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PCIE_RTD3_GPIO Rtd3Pcie2Gpio;
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PCIE_RTD3_GPIO Rtd3Pcie3Gpio;
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UINT16 DelayAfterPwrEn;
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UINT16 DelayAfterHoldReset;
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UINT8 HgSupport;
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} HG_INFO;
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//
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// VMD Info Hob
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//
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType;
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HG_INFO HgInfo;
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} HG_INFO_HOB;
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#pragma pack ()
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#endif
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