263 lines
11 KiB
C
263 lines
11 KiB
C
/** @file
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Header file for Cpu Mailbox Lib.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2014 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_MAILBOX_LIB_H_
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#define _CPU_MAILBOX_LIB_H_
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//
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// Mailbox Related Definitions
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//
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#define MAILBOX_TYPE_PCODE 0x00000001
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#define MAILBOX_TYPE_OC 0x00000002
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#define MAILBOX_TYPE_VR_MSR 0x00000003
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#define PCODE_MAILBOX_INTERFACE_OFFSET 0x5DA4
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#define PCODE_MAILBOX_DATA_OFFSET 0x5DA0
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#define PCU_CR_BCLK_FREQ_MCHBAR 0x00005F60
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#define OC_MAILBOX_MSR 0x00000150
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#define VR_MAILBOX_MSR_INTERFACE 0x00000607
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#define VR_MAILBOX_MSR_DATA 0x00000608
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#define MAILBOX_PCODE_CMD_READ_PEG_CRIO_CR 0x00000029
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#define MAILBOX_PCODE_CMD_WRITE_PEG_CRIO_CR 0x0000002A
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#define N_MAILBOX_TARGET_IO_BLOCK_OFFSET 0x18
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#define MAILBOX_PCODE_CMD_READ_C6DRAM_CONFIG 0x0000001C
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#define B_MAILBOX_BIOS_ALLOW_C6DRAM BIT0
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#define B_MAILBOX_C6DRAM_SUPPORTED BIT1
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#define MAILBOX_PCODE_CMD_WRITE_C6DRAM_CONFIG 0x0000001D
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#define MAILBOX_OC_CMD_BCLK_FREQUENCY_CMD 0x00000005
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#define MAILBOX_PCODE_CMD_BCLK_CONFIG 0x0000003F
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#define MAILBOX_PCODE_BCLK_CONFIG_SET_SSC_CONTROL_SUBCOMMAND 0x00000004
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#define MAILBOX_PCODE_BCLK_CONFIG_GET_SSC_CONTROL_SUBCOMMAND 0x00000003
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//
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// Inform Graphics Memory Config
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//
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#define BIOS_MAILBOX_INFORM_GRAPHICS_MEMORY_CONFIG 0x55
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#define SELECT_ALTERNATE_DID2 0x0
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//
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// HwP Misc Functions
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//
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#define MAILBOX_PCODE_CMD_READ_AUTONOMOUS_PARAMS 0x00000010
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#define MAILBOX_PCODE_CMD_WRITE_AUTONOMOUS_PARAMS 0x00000011
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#define MAILBOX_PCODE_CMD_READ_PCU_MISC_CONFIG 0x00000005
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#define MAILBOX_PCODE_CMD_WRITE_PCU_MISC_CONFIG 0x00000006
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#define MAILBOX_OC_CMD_READ_PER_CORE_RATIO_LIMITS_CMD 0x0000001C
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#define MAILBOX_OC_CMD_WRITE_PER_CORE_RATIO_LIMITS_CMD 0x0000001D
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//
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// MAILBOX_BIOS_CMD_MISC_ALG_CONFIG_INTERFACE command set
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//
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#define MAILBOX_PCODE_CMD_MISC_ALG_CONFIG_INTERFACE 0x2B
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#define MAILBOX_PCODE_SUBCMD_READ_HDC_DIS_WHEN_OSREQ_ABOVE_PE_SUBCOMMAND 0x00
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#define MAILBOX_PCODE_SUBCMD_WRITE_HDC_DIS_WHEN_OSREQ_ABOVE_PE_SUBCOMMAND 0x01
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#define MAILBOX_PCODE_SUBCMD_READ_EPB_PECI_CONTROL_SUBCOMMAND 0x02
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#define MAILBOX_PCODE_SUBCMD_WRITE_EPB_PECI_CONTROL_SUBCOMMAND 0x03
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#define MAILBOX_PCODE_SUBCMD_READ_RING_DISTRESS_DISABLE_SUBCOMMAND 0x04
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#define MAILBOX_PCODE_SUBCMD_WRITE_RING_DISTRESS_DISABLE_SUBCOMMAND 0x05
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#define MAILBOX_PCODE_SUBCMD_READ_RING_AUTOGV_DISABLE_SUBCOMMAND 0x08
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#define MAILBOX_PCODE_SUBCMD_WRITE_RING_AUTOGV_DISABLE_SUBCOMMAND 0x09
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#define MAILBOX_BIOS_CMD_WRITE_HSPHY_CONFIG 0x0000002D
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#define B_MAILBOX_BIOS_ALLOW_HSPHY_1 BIT0
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//
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// MAILBOX_BIOS_POWER_RAIL_SHUTDOWN_POLICY
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//
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#define MAILBOX_PCODE_CMD_BIOS_WRITE_POWER_RAIL_SHUTDOWN_POLICY 0x42
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#define B_MAILBOX_INF_DFX_PWROFF_REQ BIT0
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#define V_MAILBOX_INF_DFX_PWROFF_REQ_DIS 0 ///< INF_DFX will keep up
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#define V_MAILBOX_INF_DFX_PWROFF_REQ_EN 1 ///< INF_DFX will shutdown
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#define MAILBOX_PCODE_CMD_BIOS_READ_POWER_RAIL_SHUTDOWN_POLICY 0x43
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#ifndef MAILBOX_WAIT_TIMEOUT
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#define MAILBOX_WAIT_TIMEOUT 1000 ///< 1 millisecond
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#endif
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#ifndef MAILBOX_WAIT_STALL
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#define MAILBOX_WAIT_STALL 1 ///< 1 microsecond
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#endif
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#ifndef MAILBOX_READ_TIMEOUT
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#define MAILBOX_READ_TIMEOUT 10 ///< 10 microseconds
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#endif
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//
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// Pcode Mailbox completion codes
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//
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#define PCODE_MAILBOX_CC_SUCCESS 0x0
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#define PCODE_MAILBOX_CC_ILLEGAL_CMD 0x1
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#define PCODE_MAILBOX_CC_TIMEOUT 0x2
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#define PCODE_MAILBOX_CC_ILLEGAL_DATA 0x3
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#define PCODE_MAILBOX_CC_EDRAM_NOT_FUNCTIONAL 0x4
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#define PCODE_MAILBOX_CC_ILLEGAL_VR_ID 0x5
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#define PCODE_MAILBOX_CC_LOCKED 0x6
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#define PCODE_MAILBOX_CC_VR_ERROR 0x7
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#define PCODE_MAILBOX_CC_ILLEGAL_SUBCOMMAND 0x8
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#define PCODE_MAILBOX_CC_EDRAM_CURRENTLY_UNAVAILABLE 0xA
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#define MAILBOX_PARAM_1_OFFSET 8
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#define MAILBOX_PARAM_2_OFFSET 16
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///
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/// Expanded Overclocking Mailbox interface defintion, contains command id/completion code,
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/// input parameters and the run/busy bit
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///
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typedef union _OC_MAILBOX_INTERFACE {
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UINT32 InterfaceData; ///< All bit fields as a 32-bit value.
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///
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/// Individual bit fields.
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///
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struct {
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UINT8 CommandCompletion : 8; ///< Command ID and completion code
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UINT8 Param1 : 8; ///< Parameter 1, generally used to specify the CPU Domain ID
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UINT8 Param2 : 8; ///< Parameter 2, only current usage is as a core index for ratio limits message
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UINT8 Reserved : 7; ///< Reserved for future use
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UINT8 RunBusy : 1; ///< Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this bit after the message is consumed.
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} Fields;
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} OC_MAILBOX_INTERFACE;
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///
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/// Consolidated OC mailbox command structure containing both data and interface information
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///
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typedef struct _OC_MAILBOX_FULL {
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UINT32 Data; ///< OC Mailbox read/write data
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OC_MAILBOX_INTERFACE Interface; ///< OC mailbox interface
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} OC_MAILBOX_FULL;
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///
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/// Expanded Pcode Mailbox interface defintion, contains command id, param1, param2,
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/// and the run/busy bit
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///
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typedef union _PCODE_MAILBOX_INTERFACE {
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UINT32 InterfaceData; ///< All bit fields as a 32-bit value.
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///
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/// Individual bit fields.
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///
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struct {
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UINT32 Command : 8; ///< Pcode mailbox command
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UINT32 Param1 : 8; ///< This field contains parameter 1, used by sub-commands.
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UINT32 Param2 : 13; ///< This field contains parameter 2.
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UINT32 Reserved : 2; ///< Reserved for future use
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UINT32 RunBusy : 1; ///< Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this bit after the message is consumed.
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} Fields;
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} PCODE_MAILBOX_INTERFACE;
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///
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/// Consolidated Pcode mailbox command structure containing both data and interface information
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///
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typedef struct _PCODE_MAILBOX_FULL {
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PCODE_MAILBOX_INTERFACE Interface; ///< Pcode mailbox interface
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UINT32 Data; ///< Pcode mailbox read/write data
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} PCODE_MAILBOX_FULL;
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/**
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Generic Mailbox function for mailbox write commands. This function will
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poll the mailbox interface for control, issue the write request, poll
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for completion, and verify the write was succussful.
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@param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
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@param[in] MailboxCommand Overclocking mailbox command data
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@param[in] MailboxData Overclocking mailbox interface data
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@param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status values are:
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- SUCCESS (0) Command succeeded.
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- OC_LOCKED (1) Overclocking is locked. Service is read-only.
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- INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
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- MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
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- MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
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- OC_NOT_SUPPORTED (5) Domain does not support overclocking.
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@retval EFI_STATUS
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- EFI_SUCCESS Command succeeded.
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- EFI_INVALID_PARAMETER Invalid read data detected from pcode.
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- EFI_UNSUPPORTED Unsupported MailboxType parameter.
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**/
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EFI_STATUS
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EFIAPI
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MailboxWrite (
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IN UINT32 MailboxType,
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IN UINT32 MailboxCommand,
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IN UINT32 MailboxData,
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OUT UINT32 *MailboxStatus
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);
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/**
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Generic Mailbox function for mailbox read commands. This function will write
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the read request from MailboxType, and populate the read results in the MailboxDataPtr.
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@param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
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@param[in] MailboxCommand Overclocking mailbox command data
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@param[out] *MailboxDataPtr Pointer to the overclocking mailbox interface data
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@param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status are
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- SUCCESS (0) Command succeeded.
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- OC_LOCKED (1) Overclocking is locked. Service is read-only.
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- INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
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- MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
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- MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
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- OC_NOT_SUPPORTED (5) Domain does not support overclocking.
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@retval EFI_STATUS
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- EFI_SUCCESS Command succeeded.
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- EFI_INVALID_PARAMETER Invalid read data detected from pcode.
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- EFI_UNSUPPORTED Unsupported MailboxType parameter.
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**/
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EFI_STATUS
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EFIAPI
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MailboxRead (
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IN UINT32 MailboxType,
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IN UINT32 MailboxCommand,
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OUT UINT32 *MailboxDataPtr,
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OUT UINT32 *MailboxStatus
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);
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/**
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Poll the run/busy bit of the mailbox until available or timeout expires.
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@param[in] MailboxType
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@retval EFI_STATUS
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- EFI_SUCCESS Command succeeded.
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- EFI_TIMEOUT Command timeout.
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**/
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EFI_STATUS
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EFIAPI
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PollMailboxReady (
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IN UINT32 MailboxType
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);
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#endif
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