99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/** @file
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Header file for PEI PCIe functionality
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PEI_PCIE_LIB_H_
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#define _PEI_PCIE_LIB_H_
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extern EFI_GUID gPciImrHobGuid;
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typedef struct {
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EFI_HOB_GUID_TYPE Header;
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UINT64 PciImrBase;
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} PCI_IMR_HOB;
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/**
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Read the PCIe PreMem policy to check port number for PCIe IMR
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@retval port number
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**/
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UINT8
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GetPcieImrPortNumber (
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VOID
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);
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/**
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Read the PCIe Premem policy to see if PCIe IMR is enabled.
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@retval TRUE PCIe IMR is enabled
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@retval FALSE PCIe IMR is disabled
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**/
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BOOLEAN
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IsPcieImrEnabled (
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VOID
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);
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/**
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Read the PCIE policy to check port Location for PCIe IMR
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@retval RootPort Location
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**/
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UINT8
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GetPcieImrPortLocation (
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VOID
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);
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/**
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Read the PCIe policy to get PCIe IMR Size.
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@retval PcieImrSize Size of PCIe Imr in MB
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**/
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UINT16
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GetPcieImrSize (
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VOID
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);
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/**
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This function puts PCIe IMR related information into HOB
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@param[in] BaseLow lower 32 bits of PCIe IMR address
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@param[in] BaseHigh higher 32 bits of PCIe IMR address
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**/
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VOID
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BuildPciImrHob (
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UINT32 BaseLow,
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UINT32 BaseHigh
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);
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#endif
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