85 lines
4.1 KiB
C
85 lines
4.1 KiB
C
/**@file
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Header file of TBT MailBox Command Definition shared by C and ASL code.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2019 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#define PCIE2TBT_VLD_B BIT0
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#define TBT2PCIE_DON_R BIT0
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#define TBT_MAILBOX_DELAY 1000 ///< 1ms
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#define SET_CM_TIMEOUT_IN_MS 500 ///< 10 * TBT_MAILBOX_DELAY = 500ms
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///
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///Mailbox command value to controller is generic on all types of TBT controllers
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///
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/**
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Mailbox command to link controller (LC) and Connection Manager (CM) to enter Sx with wake support
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**/
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#define PCIE2TBT_GO2SX 0x04 //(0x02 << 1)
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/**
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Mailbox command to link controller (LC) and Connection Manager (CM) to enter Sx without wake support
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**/
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#define PCIE2TBT_GO2SX_NO_WAKE 0x06 //(0x03 << 1)
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/**
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Mailbox command to controller to exit Sx and the system went to sleep with attached devices previously
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**/
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#define PCIE2TBT_SX_EXIT_TBT_CONNECTED 0x08 //(0x04 << 1)
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#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED 0x0A //(0x05 << 1)
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#define PCIE2TBT_OS_UP 0x0C //(0x06 << 1)
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#define PCIE2TBT_SET_SECURITY_LEVEL 0x10 //(0x08 << 1)
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#define PCIE2TBT_GET_SECURITY_LEVEL 0x12 //(0x09 << 1)
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#define PCIE2TBT_CM_AUTH_MODE_ENTER 0x20 //(0x10 << 1)
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#define PCIE2TBT_CM_AUTH_MODE_EXIT 0x22 //(0x11 << 1)
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#define PCIE2TBT_BOOT_ON 0x30 //(0x18 << 1)
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#define PCIE2TBT_BOOT_OFF 0x32 //(0x19 << 1)
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#define PCIE2TBT_USB_ON 0x32 //(0x19 << 1)
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#define PCIE2TBT_GET_ENUMERATION_METHOD 0x34 //(0x1A << 1)
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#define PCIE2TBT_SET_ENUMERATION_METHOD 0x36 //(0x1B << 1)
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#define PCIE2TBT_POWER_CYCLE 0x38 //(0x1C << 1)
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/**
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Mailbox command to CM to ensure all connected TBT devices are available on PCIe
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**/
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#define PCIE2TBT_CONNECT_TOPOLOGY_COMMAND 0x3E //(0x1F << 1)
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#define PCIE2TBT_FIRMWARE_CM_MODE 0x44 //(0x22 << 1)
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#define PCIE2TBT_PASS_THROUGH_MODE 0x46 //(0x23 << 1)
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#define PCIE2TBT_GO_2_SLEEP 0x48 //(0x24 << 1)
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/**
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Extra data of mailbox command
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**/
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#define ENABLE_PCIE_TUNNELING_FOR_USB4 0x0
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#define DISABLE_PCIE_TUNNELING_FOR_USB4 0x5
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/**
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Mailbox command to program DMA 0/1 SSID SVID
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**/
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#define PCIE2TBT_SSID_SVID_CFG 0x60 //(0x30 << 1)
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#define PCIE2TBT_SSID_SVID_DATA_OFFSET 0xF4 |