154 lines
7.1 KiB
C
154 lines
7.1 KiB
C
/** @file
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This file contains definitions of TCSS Data.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _TCSS_DATA_HOB_H_
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#define _TCSS_DATA_HOB_H_
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#include <Base.h>
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#include <TcssInfo.h>
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#include <ConfigBlock.h>
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#include <ConfigBlock/SiConfig.h>
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extern EFI_GUID gTcssHobGuid;
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extern EFI_GUID gTcssSsidHobGuid;
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//
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// CM mode in Pre-boot - bit 2:0
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//
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#define USB4_CM_MODE_FW_CM 0x00
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#define USB4_CM_MODE_SW_CM 0x01
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//
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// CM mode switch unsupport bit - bit 3
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//
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#define USB4_CM_MODE_SWITCH_UNSUPPORTED 0x08
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//
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// CM mode setup option - bit 2:0
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//
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#define SETUP_OPTION_USB4_CM_MODE_FW 0x00
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#define SETUP_OPTION_USB4_CM_MODE_SW 0x01
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#define SETUP_OPTION_USB4_CM_MODE_OS 0x02
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#define SETUP_OPTION_USB4_CM_MODE_THROUGH 0x03
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#pragma pack (push,1)
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///
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/// Structure for Tbt firmware status from IMR.
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///
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typedef union {
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UINT32 RegValue;
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struct {
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UINT32 TbtFwVersion:16; ///< Bits 15:0
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UINT32 Reserved:6; ///< Bits 21:16
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UINT32 ErrorCode:8; ///< Bits 29:22
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UINT32 Valid:1; ///< Bits 30 - 00 = untrusted FW, 01 = successful authentication
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UINT32 Done:1; ///< Bits 31 - 01 = FW download to IMR is done
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} Bits;
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} TBT_IMR_STATUS;
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///
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/// Structure for MG image status from IMR.
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///
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typedef union {
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UINT32 RegValue;
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struct {
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UINT32 MgFwVersion:16; ///< Bits 15:0
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UINT32 Reserved:6; ///< Bits 21:16
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UINT32 ErrorCode:8; ///< Bits 29:22
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UINT32 Valid:1; ///< Bits 30 - 00 = untrusted FW, 01 = successful authentication
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UINT32 Done:1; ///< Bits 31 - 01 = FW download to IMR is done
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} Bits;
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} MG_IMR_STATUS;
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/**
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TCSS data definition
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**/
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typedef struct {
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UINT32 IOMReady:1; ///< Indicate the IOM ready.
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UINT32 PcieMultipleSegmentEnabled:1; /// Deprecate < Indicate the extra segment of iTBT PCIe is enabled or not.
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UINT32 Rsvd:30; ///< Reserved for future use.
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UINT32 IomFwVersion; ///< IOM FW version.
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UINT32 IomFwEngrVersion; ///< IOM FW Engineer version. Non-zero value used to identify engineering versions / hotfixes. Shall be zero for official releases.
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TBT_IMR_STATUS TbtImrStatus; ///< Tbt FW IMR Status.
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UINT32 ItbtPcieSegMap; ///< iTBT PCIE RP 0-3 Segment Map
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UINT32 ItbtPcieFuncMap; ///< iTBT PCIE RP 0-3 Function Map
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UINT8 ItbtPcieRpEn[MAX_ITBT_PCIE_PORT]; ///< ItbtPcieRpEn PCIE RP Device Enable
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UINT8 ItbtXhciEn; ///< ItbtPcieRpEn XHCI Device Enable
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UINT8 ItbtXdciEn; ///< ItbtPcieRpEn XDCI Device Enable
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UINT8 ItbtDmaEn[MAX_HOST_ITBT_DMA_NUMBER]; ///< ItbtPcieRpEn DMA Device Enable
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UINT8 TcssxDCIInt; ///< iTBT xDCI Int Pin number
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UINT8 TcssxDCIIrq; ///< iTBT xDCI APIC IRQ number
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UINT8 TcssRtd3; ///< TCSS RTD3
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UINT8 ItbtForcePower; ///< iTBT Force Power status
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MG_IMR_STATUS MgImrStatus; ///< MG IMR Status
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UINT8 TcssIomVccSt; ///< IOM VCCST request.
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UINT8 DeepstTcState; ///< Maximum TC C State limit
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} TCSS_DATA;
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typedef struct {
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UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
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UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting, Max Snoop Latency.
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UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting, Max Non-Snoop Latency.
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UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Snoop Latency Override Mode.
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UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Snoop Latency Override Multiplier.
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UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Snoop Latency Override Value.
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UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
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UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
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UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Value.
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UINT8 ForceLtrOverride; ///< <b>0: Disable</b>; 1: Enable.
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UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
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} ITBT_PCILTR_DATA;
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///
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/// TCSS Data Hob
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///
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gTcssHobGuid
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TCSS_DATA TcssData; ///< Offset 24 TCSS data definition.
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ITBT_PCILTR_DATA PcieItbtLtrData[MAX_ITBT_PCIE_PORT];
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} TCSS_DATA_HOB;
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///
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/// TCSS SSID Data Hob
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///
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID
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SVID_SID_SKIP_TABLE *TcssSsidTable; ///< TCSS SSID table
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UINT16 NumberOfTcssSsidTable; ///< number of TCSS SSID table
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UINT8 Reserved[2]; ///< Reserved for Hob size allignment
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} TCSS_DATA_SSID_HOB;
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#pragma pack (pop)
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#endif
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