154 lines
5.0 KiB
C
154 lines
5.0 KiB
C
/** @file
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This file contains definitions of PCIe controller information
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_PCIE_INFO_H_
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#define _CPU_PCIE_INFO_H_
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#define PCIE_HWEQ_COEFFS_MAX 5
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/**
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PCIe controller configuration.
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**/
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#define CPU_PCIE_1x16 7
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#define CPU_PCIE_1x8_2x4 4
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#define CPU_PCIE_2x8 5
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#define CPU_PCIE_1x4 0
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//
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// Device 1 Memory Mapped IO Register Offset Equates
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//
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#define SA_PEG_BUS_NUM 0x00
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#define SA_PEG_DEV_NUM 0x01
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#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM
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#define SA_PEG0_FUN_NUM 0x00
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#define SA_PEG1_DEV_NUM SA_PEG_DEV_NUM
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#define SA_PEG1_FUN_NUM 0x01
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#define SA_PEG2_DEV_NUM SA_PEG_DEV_NUM
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#define SA_PEG2_FUN_NUM 0x02
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#define SA_PEG3_DEV_NUM 0x06
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#define SA_PEG3_FUN_NUM 0x00
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#define V_SA_PEG_VID 0x8086
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#define V_PH3_FS_CR_OVR 0x3E
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#define B_PH3_FS_CR_OVR_EN BIT8
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#define V_PH3_LF_CR_OVR 0x14
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#define B_PH3_LF_CR_OVR_EN BIT16
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//
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// Temporary Device & Function Number used for Switchable Graphics DGPU
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//
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#define SA_TEMP_DGPU_DEV 0x00
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#define SA_TEMP_DGPU_FUN 0x00
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//
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// SA PCI Express* Port configuration
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//
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#define CPU_PCIE_MAX_ROOT_PORTS 4
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#define CPU_PCIE_MAX_CONTROLLERS 3
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#define SA_PEG_MAX_FUN 0x04
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#define SA_PEG_MAX_LANE 0x14
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#define SA_PEG_MAX_BUNDLE 0x0A
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#define SA_PEG_MAX_FUN_GEN3 0x03
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#define SA_PEG_MAX_LANE_GEN3 0x10
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#define SA_PEG_MAX_BUNDLE_GEN3 0x08
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#define SA_PEG0_CNT_MAX_LANE 0x10
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#define SA_PEG0_CNT_MAX_BUNDLE 0x08
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#define SA_PEG0_CNT_FIRST_LANE 0x00
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#define SA_PEG0_CNT_FIRST_BUNDLE 0x00
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#define SA_PEG0_CNT_LAST_LANE 0x0F
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#define SA_PEG0_CNT_LAST_BUNDLE 0x07
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#define SA_PEG3_CNT_MAX_LANE 0x04
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#define SA_PEG3_CNT_MAX_BUNDLE 0x02
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#define SA_PEG3_CNT_FIRST_LANE 0x00
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#define SA_PEG3_CNT_FIRST_BUNDLE 0x00
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#define SA_PEG3_CNT_LAST_LANE 0x03
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#define SA_PEG3_CNT_LAST_BUNDLE 0x01
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#define SA_PEG3_CNT_MAX_LANE_GEN3 0x00
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#define SA_PEG3_CNT_MAX_BUNDLE_GEN3 0x00
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#define SA_PEG3_CNT_FIRST_LANE_GEN3 0x00
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#define SA_PEG3_CNT_FIRST_BUNDLE_GEN3 0x00
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#define SA_PEG3_CNT_LAST_LANE_GEN3 0x00
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#define SA_PEG3_CNT_LAST_BUNDLE_GEN3 0x00
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//
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// Silicon and SKU- specific MAX defines
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//
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#define SA_PEG_CNL_H_MAX_FUN SA_PEG_MAX_FUN // CNL-H- SKU supports 4 controllers with 20 PEG lanes and 10 bundles
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#define SA_PEG_CNL_H_MAX_LANE SA_PEG_MAX_LANE
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#define SA_PEG_CNL_H_MAX_BUNDLE SA_PEG_MAX_BUNDLE
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#define SA_PEG_NON_CNL_H_MAX_FUN 0x03 // All non-CNL-H- SKU supports 3 controllers with 16 PEG lanes and 8 bundles
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#define SA_PEG_NON_CNL_H_MAX_LANE 0x10
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#define SA_PEG_NON_CNL_H_MAX_BUNDLE 0x08
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#define DMI_AUTO 0
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#define DMI_GEN1 1
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#define DMI_GEN2 2
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#define DMI_GEN3 3
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#define PH3_METHOD_AUTO 0x0
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#define PH3_METHOD_HWEQ 0x1
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#define PH3_METHOD_SWEQ 0x2
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#define PH3_METHOD_STATIC 0x3
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#define PH3_METHOD_DISABLED 0x4
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#define MAX_PRESETS 9
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#define BEST_PRESETS 4
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//
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// The PEG Disable Mask BIT0 ~ BIT3 for PEG0 ~ PEG3
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//
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#define V_PEG_DISABLE_MASK 0x0F
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#define B_PEG0_DISABLE_MASK BIT0
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#define B_PEG1_DISABLE_MASK BIT1
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#define B_PEG2_DISABLE_MASK BIT2
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#define B_PEG3_DISABLE_MASK BIT3
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#define CPU_PCIE_CTRL_060 0
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#define CPU_PCIE_CTRL_010 1
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#define CPU_PCIE_CTRL_011_012 2
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//
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// SIP version
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//
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#define PCIE_SIP16 0
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#define PCIE_SIP17 1
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#endif
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