75 lines
2.7 KiB
C
75 lines
2.7 KiB
C
/** @file
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Header file for HSIO handle
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification
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**/
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#ifndef _HSIO_HANDLE_H_
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#define _HSIO_HANDLE_H_
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#include <ConfigBlock.h>
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#include <HsioConfig.h>
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#include <HsioPcieConfig.h>
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#include <HsioSataConfig.h>
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#include <HsioLane.h>
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/**
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Internal HSIO policy options
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**/
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typedef struct {
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/**
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This is internal switch which allow skip updating Chipset Init table from IP block flow
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EBG is not supporting updating SUS tables.
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**/
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BOOLEAN SkipWriteToChipsetInitTable;
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/**
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Specifies the Pcie Pll Spread Spectrum Percentage
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TODO: move this option to HSIO config block
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**/
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UINT8 PciePllSsc;
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} HSIO_PRIVATE_CONFIG;
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/**
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HSIO device structure
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Stores all data necessary to initialize HSIO IP block
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**/
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typedef struct {
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HSIO_LANE *Lane;
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USB3_HSIO_CONFIG *Usb3HsioConfig;
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PCH_HSIO_SATA_PREMEM_CONFIG *SataLanePreMemConfig;
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PCH_HSIO_PCIE_PREMEM_CONFIG *PcieLanePreMemConfig;
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HSIO_PRIVATE_CONFIG *PrivateConfig;
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PCH_HSIO_CONFIG *HsioConfig;
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} HSIO_HANDLE;
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#endif // _HSIO_HANDLE_H_
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