108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
/** @file
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This file contains definitions of Hybrid Graphics information
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _HYBRID_GRAPHICS_INFO_H_
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#define _HYBRID_GRAPHICS_INFO_H_
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///
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/// HgMode settings
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///
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typedef enum {
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HgModeDisabled = 0,
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HgModeReserved,
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HgModeMuxless,
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HgModeDgpu,
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HgModeMax
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} HG_MODE;
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///
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/// Hybrid Graphics defines.
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///
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#define CONVENTIONAL_MEMORY_TOP 0xA0000 ///< 640 KB
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#define BIN_FILE_SIZE_MAX 0x10000
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#define OPTION_ROM_SIGNATURE 0xAA55
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///
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/// PCIe Capability Equates
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///
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#define PCIE_CAP_ID 0x10
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#define GP_ENABLE 1
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#define GP_DISABLE 0
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef HIGH
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#define HIGH 1
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#endif
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#ifndef LOW
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#define LOW 0
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#endif
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#define HG_DELAY_HOLD_RST 100 * STALL_ONE_MILLI_SECOND
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#define HG_DELAY_PWR_ENABLE 300 * STALL_ONE_MILLI_SECOND
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#pragma pack(1)
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typedef struct {
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UINT16 Signature; ///< 0xAA55
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UINT8 Reserved[22];
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UINT16 PcirOffset;
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} VBIOS_OPTION_ROM_HEADER;
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#pragma pack()
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#pragma pack(1)
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typedef struct {
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UINT32 Signature; ///< "PCIR"
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UINT16 VendorId;
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UINT16 DeviceId;
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UINT16 Reserved0;
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UINT16 Length;
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UINT8 Revision;
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UINT8 ClassCode[3];
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UINT16 ImageLength;
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UINT16 CodeRevision;
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UINT8 CodeType;
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UINT8 Indicator;
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UINT16 Reserved1;
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} VBIOS_PCIR_STRUCTURE;
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#pragma pack()
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#endif
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