199 lines
7.8 KiB
C
199 lines
7.8 KiB
C
/** @file
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Header file for overclocking definitions.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _OC_DEFINES_H_
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#define _OC_DEFINES_H_
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//
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// OC Mailbox MSR
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//
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#define MSR_OC_MAILBOX 0x00000150
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//
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// OC Mailbox commands
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//
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#define MAILBOX_OC_CMD_GET_OC_CAPABILITIES 0x01
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#define MAILBOX_OC_CMD_GET_PER_CORE_RATIO_LIMIT 0x02
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#define MAILBOX_OC_CMD_GET_DDR_CAPABILITIES 0x03
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#define MAILBOX_OC_CMD_GET_VR_TOPOLOGY 0x04
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#define MAILBOX_OC_CMD_GET_FUSED_P0_RATIO_VOLTAGE 0x07
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#define MAILBOX_OC_CMD_GET_VOLTAGE_FREQUENCY 0x10
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#define MAILBOX_OC_CMD_SET_VOLTAGE_FREQUENCY 0x11
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#define MAILBOX_OC_CMD_GET_MISC_GLOBAL_CONFIG 0x14
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#define MAILBOX_OC_CMD_SET_MISC_GLOBAL_CONFIG 0x15
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#define MAILBOX_OC_CMD_GET_ICCMAX 0x16
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#define MAILBOX_OC_CMD_SET_ICCMAX 0x17
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#define MAILBOX_OC_CMD_GET_MISC_TURBO_CONTROL 0x18
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#define MAILBOX_OC_CMD_SET_MISC_TURBO_CONTROL 0x19
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#define MAILBOX_OC_CMD_GET_AVX_RATIO_OFFSET 0x1A
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#define MAILBOX_OC_CMD_SET_AVX_RATIO_OFFSET 0x1B
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#define MAILBOX_OC_CMD_GET_AVX_VOLTAGE_GUARDBAND 0x20
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#define MAILBOX_OC_CMD_SET_AVX_VOLTAGE_GUARDBAND 0x21
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#define MAILBOX_OC_CMD_GET_OC_TVB_CONFIG 0x24
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#define MAILBOX_OC_CMD_SET_OC_TVB_CONFIG 0x25
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//
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// PCODE Mailbox OC Interface 0x37 command set
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//
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#define MAILBOX_OC_CMD_OC_INTERFACE 0x00000037
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#define MAILBOX_OC_SUBCMD_READ_OC_MISC_CONFIG 0x00000000
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#define MAILBOX_OC_SUBCMD_WRITE_OC_MISC_CONFIG 0x00000001
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#define MAILBOX_OC_SUBCMD_READ_OC_PERSISTENT_OVERRIDES 0x00000002
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#define MAILBOX_OC_SUBCMD_WRITE_OC_PERSISTENT_OVERRIDES 0x00000003
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#define MAILBOX_OC_SUBCMD_READ_TJ_MAX_OFFSET 0x00000004
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#define MAILBOX_OC_SUBCMD_WRITE_TJ_MAX_OFFSET 0x00000005
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#define MAILBOX_OC_SUBCMD_READ_PLL_VCC_TRIM_OFFSET 0x00000006
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#define MAILBOX_OC_SUBCMD_WRITE_PLL_VCC_TRIM_OFFSET 0x00000007
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#define MAILBOX_OC_SUBCMD_READ_PVD_RATIO_THRESHOLD_OVERRIDE 0x00000008
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#define MAILBOX_OC_SUBCMD_WRITE_PVD_RATIO_THRESHOLD_OVERRIDE 0x00000009
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#define MAILBOX_OC_SUBCMD_READ_DISABLED_IA_CORES_MASK 0x0000000E
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#define MAILBOX_OC_SUBCMD_WRITE_DISABLED_IA_CORES_MASK 0x0000000F
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#define MAILBOX_OC_SUBCMD_READ_PLL_MAX_BANDING_RATIO_OVERRIDE 0x00000010
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#define MAILBOX_OC_SUBCMD_WRITE_PLL_MAX_BANDING_RATIO_OVERRIDE 0x00000011
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//
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// OC Interface (0x37) Sub-Command definitions
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//
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#define PLL_MAX_BANDING_RATIO_MINIMUM 1
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#define PLL_MAX_BANDING_RATIO_MAXIMUM 120
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#define PLL_MAX_BANDING_RATIO_MASK 0x000000FF
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//
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// OC Mailbox completion codes
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//
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#define MAILBOX_OC_COMPLETION_CODE_SUCCESS 0x00
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#define MAILBOX_OC_COMPLETION_CODE_OC_LOCKED 0x01
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#define MAILBOX_OC_COMPLETION_CODE_INVALID_DOMAIN 0x02
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#define MAILBOX_OC_COMPLETION_CODE_MAX_RATIO_EXCEEDED 0x03
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#define MAILBOX_OC_COMPLETION_CODE_MAX_VOLTAGE_EXCEEDED 0x04
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#define MAILBOX_OC_COMPLETION_CODE_OC_NOT_SUPPORTED 0x05
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#define MAILBOX_OC_COMPLETION_CODE_WRITE_FAILED 0x06
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#define MAILBOX_OC_COMPLETION_CODE_READ_FAILED 0x07
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//
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// Domain ID definitions
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//
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#define MAILBOX_OC_DOMAIN_ID_DDR 0x00
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#define MAILBOX_OC_DOMAIN_ID_IA_CORE 0x00
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#define MAILBOX_OC_DOMAIN_ID_GT 0x01
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#define MAILBOX_OC_DOMAIN_ID_RING 0x02
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#define MAILBOX_OC_DOMAIN_ID_RESERVED 0x03
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#define MAILBOX_OC_DOMAIN_ID_SYSTEM_AGENT 0x04
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#define MAILBOX_OC_DOMAIN_ID_L2_ATOM 0x05
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#define MAILBOX_OC_DOMAIN_ID_MEMORY_CONTROLLER 0x06
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//
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// BCLK Source
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//
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#define SOC_BCLK 0x00
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#define CPU_BCLK 0x01
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#define PCH_BCLK 0x02
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//
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// BCLK Select
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//
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#define SOC_BCLK_SELECT 0x0
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#define CPU_BCLK_SELECT 0x2
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//
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// PVD and FLL override definitions
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//
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#define PVD_OVERRIDES 0
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#define FLL_OVERRIDES 1
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//
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// Bit 10 is the S11.0.10V sign bit
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//
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#define FIXED_POINT_SIGN_BIT_MASK 0x0400
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#define INT16_SIGN_BIT_MASK 0x8000
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//
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// Voltage Conversion defines
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//
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#define MILLIVOLTS_PER_VOLT 1000
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#define MAX_TARGET_MV 4095
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#define MAX_OFFSET_MV 500
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#define CONVERT_TO_FIXED_POINT_VOLTS 0
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#define CONVERT_TO_BINARY_MILLIVOLT 1
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//
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// Masks and offsets
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//
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#define BIT0_MASK 0x1
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#define MAX_RATIO_MASK 0x000000FF
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#define VOLTAGE_TARGET_MASK 0x000FFF00
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#define VOLTAGE_TARGET_OFFSET 8
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#define VOLTAGE_MODE_MASK 0x00100000
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#define VOLTAGE_MODE_OFFSET 20
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#define VOLTAGE_OFFSET_MASK 0xFFE00000
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#define VOLTAGE_OFFSET_OFFSET 21
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#define QCLK_RATIO_MASK 0x000000FF
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#define MC_REF_CLK_MASK 0x00000100
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#define MC_REF_CLK_OFFSET 8
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#define NUM_DDR_CHANNELS_MASK 0x00000C00
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#define NUM_DDR_CHANNELS_OFFSET 10
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#define OC_CAPS_MAX_RATIO_MASK 0x000000FF
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#define OC_CAPS_RATIO_SUPPORT_MASK 0x00000100
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#define OC_CAPS_RATIO_SUPPORT_OFFSET 8
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#define OC_CAPS_OVERRIDE_SUPPORT_MASK 0x00000200
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#define OC_CAPS_OVERRIDE_SUPPORT_OFFSET 9
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#define OC_CAPS_OFFSET_SUPPORT_MASK 0x00000400
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#define OC_CAPS_OFFSET_SUPPORT_OFFSET 10
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#define AVX2_RATIO_OFFSET_MASK 0x000003E0
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#define AVX2_RATIO_OFFSET_OFFSET 5
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#define MISC_TURBO_RING_DOWNBIN_MASK 0x00000002
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#define MISC_TURBO_RING_DOWNBIN_OFFSET 1
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#define MISC_TURBO_TVB_RATIO_MASK 0x00000004
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#define MISC_TURBO_TVB_RATIO_OFFSET 2
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#define MISC_TURBO_TVB_VOLTAGE_MASK 0x00000008
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#define MISC_TURBO_TVB_VOLTAGE_OFFSET 3
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#define MISC_TURBO_ETVB_MASK 0x00000010
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#define MISC_TURBO_ETVB_OFFSET 4
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#define FUSED_P0_RATIO_MASK 0x000000FF
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#define FUSED_P0_VOLTAGE_MASK 0x000FFF00
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#define FUSED_P0_VOLTAGE_OFFSET 8
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#define MISC_GLOBAL_PER_CORE_VOLTAGE_MASK 0x00000008
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#define MISC_GLOBAL_PER_CORE_VOLTAGE_OFFSET 3
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#define MISC_GLOBAL_BCLK_ADAPTIVE_OFFSET 2
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#define MISC_GLOBAL_CFG_COMMAND_MASK 0x0000000F
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#define OC_MISC_CFG_MEM_REALTIME_CHG_MASK 0x00000002
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// VR Type
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#define SVID_VR 0
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#define NON_SVID_VR 1
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#endif
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