123 lines
4.1 KiB
C
123 lines
4.1 KiB
C
/** @file
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Header file for P2SB handle
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020-2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification
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**/
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#ifndef _P2SB_HANDLE_H_
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#define _P2SB_HANDLE_H_
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#include <ConfigBlock.h>
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#include <P2sbConfig.h>
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#include <P2SbController.h>
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/**
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Internal P2SB policy options
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**/
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typedef struct {
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/**
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Enable HSLE Workaround to avoid p2sb clock gating by adding 100ms delay
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**/
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BOOLEAN HsleWorkaround;
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/**
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Set to enable low latency of legacy IO.
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Some systems require lower IO latency irrespective of power.
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This is a tradeoff between power and IO latency.
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@note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
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and ITSS Clock Gating are forced to disabled.
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<b>FALSE: Disable</b>, TRUE: Enable
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**/
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BOOLEAN LegacyIoLowLatency;
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/**
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On server PCHs "Hardware Autonomous Enable" has to be always disabled.
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This flag allow to skip programming Hardware Autonomous Enable bit
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in Power Control Enable (PCE) at offset E4h P2SB config space register.
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<b>FALSE: Disable</b>, TRUE: Enable
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**/
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BOOLEAN HaPowerGatingSupported;
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/**
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If enabled, sets DPEE, CPEE and DPPEE bits to enable parity error handling
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**/
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BOOLEAN EnableParityCheck;
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/**
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This option disables Integrated Embedded Controller (IEC)
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and then LPC Fixed IO routing to IEC
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(write 0 to LFIORIEC register)
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<b>FALSE: IEC enabled</b>, TRUE: IEC disabled
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**/
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BOOLEAN IecSupportDisable;
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/**
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Allow avoid HPET and APIC BDFs to be programmed.
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<b>FALSE: BDF is programmed</b>, TRUE: BDF is not programmed
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**/
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BOOLEAN DisableHpetAndApicBdfProgramming;
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/**
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Register Endpoint Mask 7 bitfield
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Allow disable particular IOSF-SB endpoints.
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**/
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UINT32 EndpointMask7;
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} P2SB_PRIVATE_CONFIG;
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/**
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Get list of P2sb Endpoint Masked PIDs
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@param[out] EndpointMaskTable Endpoint Masked PIDs
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@param[out] EndpointMaskTableLength Length of EndpointMaskTable
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**/
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typedef
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VOID
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(*P2SB_GET_ENDPOINT_MASKED_PIDS) (
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OUT UINT16 **EndpointMaskTable,
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OUT UINT32 *EndpointMaskTableLength
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);
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/**
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P2SB callbacks
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List of function pointers can passed to IB Block driver
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**/
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typedef struct {
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P2SB_GET_ENDPOINT_MASKED_PIDS GetEndpointMaskedPids;
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} P2SB_CALLBACK;
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/**
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GBE device structure
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Stores all data necessary to initialize GBE IP block
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**/
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typedef struct {
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P2SB_CONTROLLER *Controller;
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PCH_P2SB_CONFIG *P2SbConfig;
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P2SB_PRIVATE_CONFIG *PrivateConfig;
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P2SB_CALLBACK *Callback;
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} P2SB_HANDLE;
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#endif // _P2SB_HANDLE_H_
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