355 lines
12 KiB
Plaintext
355 lines
12 KiB
Plaintext
/** @file
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This file contains the PCIe Root Port Common configuration
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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External(PINI, MethodObj) // Platform specific PCIe root port initialization.
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External(\_SB.PC00.PC2M, MethodObj)
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External(PPBA, MethodObj) // PCIe power budget allocation
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External(UPRD, MethodObj) // PCIe update PERST# assertion delay
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External(PPS0, MethodObj) // Platform specific PCIe root port _PS0 Hook Function.
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External(PPS3, MethodObj) // Platform specific PCIe root port _PS3 Hook Function.
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Name (PRTP, PCIE_RP_TYPE_PCH) // PCIE RP TYPE
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OperationRegion(PXCS,SystemMemory,\_SB.PC00.PC2M(_ADR()),0x480)
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Field(PXCS,AnyAcc, NoLock, Preserve)
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{
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Offset(0),
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VDID, 32,
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Offset(0x50), // LCTL - Link Control Register
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L0SE, 1, // 0, L0s Entry Enabled
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, 3,
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LDIS, 1,
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, 3,
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Offset(0x52), // LSTS - Link Status Register
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, 13,
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LASX, 1, // 0, Link Active Status
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Offset(0x5A), // SLSTS[7:0] - Slot Status Register
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ABPX, 1, // 0, Attention Button Pressed
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, 2,
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PDCX, 1, // 3, Presence Detect Changed
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, 2,
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PDSX, 1, // 6, Presence Detect State
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, 1,
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Offset(0x60), // RSTS - Root Status Register
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, 16,
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PSPX, 1, // 16, PME Status
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Offset(0xA4), // PMCSR
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D3HT, 2, // PowerState
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Offset(R_PCH_PCIE_CFG_MPC), // 0xD8, MPC - Miscellaneous Port Configuration Register
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, 30,
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HPEX, 1, // 30, Hot Plug SCI Enable
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PMEX, 1, // 31, Power Management SCI Enable
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Offset(R_PCH_PCIE_CFG_SPR), // 0xE0, SPR - Scratch Pad Register
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SCB0, 1, // Scratchpad register SPR[0] (SCB)
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, 6,
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NCB7, 1, // Non-Sticky Scratch Pad Bit (NSCB)[7]
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Offset(R_PCH_PCIE_CFG_RPPGEN), // 0xE2, RPPGEN - Root Port Power Gating Enable
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, 2,
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L23E, 1, // 2, L23_Rdy Entry Request (L23ER)
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L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
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Offset(0x328), // 0x328, PCI Express Status 1
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, 19,
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LNKS, 4, // Link Status
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}
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Field(PXCS,AnyAcc, NoLock, WriteAsZeros)
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{
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Offset(R_PCH_PCIE_CFG_SMSCS), // 0xDC, SMSCS - SMI/SCI Status Register
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, 30,
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HPSX, 1, // 30, Hot Plug SCI Status
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PMSX, 1 // 31, Power Management SCI Status
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}
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//
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// L23D method recovers link from L2 or L3 state. Used for RTD3 flows, right after endpoint is powered up and exits reset.
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// This flow is implemented in ASL because rootport registers used for L2/L3 entry/exit
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// are proprietary and OS drivers don't know about them.
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//
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Method (L23D, 0, Serialized) {
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If (LLess (SIPV, 16)) {
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If(LNotEqual(NCB7,0x1)) {
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Return()
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}
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} Else {
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If(LNotEqual(SCB0,0x1)) {
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Return()
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}
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}
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/// Set L23_Rdy to Detect Transition (L23R2DT)
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Store(1, L23R)
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Store(0, Local0)
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/// Wait for transition to Detect
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While(L23R) {
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If(Lgreater(Local0, 4))
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{
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Break
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}
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Sleep(16)
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Increment(Local0)
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}
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If (LLess (SIPV, 16)) {
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Store(0, NCB7)
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} Else {
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Store(0, SCB0)
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}
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/// Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms)
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/// Worst case per PCIe spec from Detect to Link Active is:
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/// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (24+2+2+2+2)
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Store(0, Local0)
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While(LEqual(LASX,0)) {
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If(Lgreater(Local0, 8))
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{
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Break
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}
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Sleep(16)
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Increment(Local0)
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}
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}
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//
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// DL23 method puts link to L2 or L3 state. Used for RTD3 flows, before endpoint is powered down.
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// This flow is implemented in ASL because rootport registers used for L2/L3 entry/exit
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// are proprietary and OS drivers don't know about them.
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//
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Method (DL23, 0, Serialized) {
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Store(1, L23E)
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Sleep(16)
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Store(0, Local0)
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While(L23E) {
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If(Lgreater(Local0, 4))
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{
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Break
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}
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Sleep(16)
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Increment(Local0)
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}
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If (LLess (SIPV, 16)) {
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Store(1, NCB7)
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} Else {
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Store(1, SCB0)
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}
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}
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Name(LTRV, Package(){0,0,0,0})
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Name(HBCS, 0) // Hybrid connection status
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Name(PRMV, 0) // PCIE Rp Mapped under VMD
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Name(RD3C, 2) // 2: D3Cold support for Storage connected to PCIE port, 1: D3Hot support for Storage connected to PCIE port,
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// 0: D3 unsupport for Storage connected to PCIE port. By default this is set as 2 for other EndPoints
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//
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// Check if root port is present.
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// @return 0: root port is disabled, 1: root port is enabled
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//
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Method(PRES) {
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If (LEqual (VDID, 0xFFFFFFFF)) {
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Return(0)
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} Else {
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Return(1)
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}
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}
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//
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// _DSM Device Specific Method
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//
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// Arg0: UUID Unique function identifier
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// Arg1: Integer Revision Level
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// Arg2: Integer Function Index (0 = Return Supported Functions)
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// Arg3: Package Parameters
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Method(_DSM, 4, Serialized) {
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//
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// Switch based on which unique function identifier was passed in
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//
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If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
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//
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// _DSM Definitions for Latency Tolerance Reporting
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//
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// Arguments:
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// Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
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// Arg1: Revision ID: 2
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// Arg2: Function Index: 1, 6
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// Arg3: Empty Package
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//
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// Return:
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// A Package of four integers corresponding with the LTR encoding defined
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// in the PCI Express Base Specification, as follows:
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// Integer 0: Maximum Snoop Latency Scale
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// Integer 1: Maximum Snoop Latency Value
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// Integer 2: Maximum No-Snoop Latency Scale
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// Integer 3: Maximum No-Snoop Latency Value
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// These values correspond directly to the LTR Extended Capability Structure
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// fields described in the PCI Express Base Specification.
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//
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//
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// Switch by function index
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//
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Switch(ToInteger(Arg2)) {
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//
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// Function Index:0
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// Standard query - A bitmask of functions supported
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//
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Case (0) {
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Name(OPTS,Buffer(2){0,0})
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CreateBitField(OPTS,0,FUN0)
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CreateBitField(OPTS,6,FUN6)
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CreateBitField(OPTS,8,FUN8)
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CreateBitField(OPTS,9,FUN9)
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CreateBitField(OPTS,10,FUNA)
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CreateBitField(OPTS,11,FUNB)
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if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
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Store(1,FUN0)
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if (LNotEqual (LTEN, 0)) {
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Store(1,FUN6)
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}
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If(CondRefOf(ECR1)) {
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if(LEqual(ECR1,1)){
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if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID: 3
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Store(1,FUN8)
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Store(1,FUN9)
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}
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}
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}
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}
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If (LGreaterEqual(Arg1, 4)) { //test Arg1 for Revision ID: 4
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If(CondRefOf(PPBA)) {
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Store(1,FUNA)
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}
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If(CondRefOf(UPRD)) {
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Store(1,FUNB)
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}
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}
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Return (OPTS)
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}
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//
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// Function Index: 6
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// LTR Extended Capability Structure
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//
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Case(6) {
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if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
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Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0))
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Store(And(LMSL,0x3FF), Index(LTRV, 1))
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Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2))
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Store(And(LNSL,0x3FF), Index(LTRV, 3))
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Return (LTRV)
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}
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}
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Case(8) { //ECR ACPI additions for FW latency optimizations, DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume
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If(CondRefOf(ECR1)) {
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if(LEqual(ECR1,1)){
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if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
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return (1)
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}
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}
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}
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}
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Case(9) { //ECR ACPI additions for FW latency optimizations, DSM for Specifying Device Readiness Durations
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If(CondRefOf(ECR1)) {
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if(LEqual(ECR1,1)){
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if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
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return(Package(5){50000,Ones,Ones,50000,Ones})
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}
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}
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}
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}
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//
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// Function index 10 - negotiate device auxilary power consumption.
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//
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Case(10) {
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If(CondRefOf(PPBA)) {
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Return(PPBA(Arg3))
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}
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}
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//
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// Function index 11 update delay between PME_TO_Ack and PERST# assertion
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//
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Case(11) {
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If(CondRefOf(UPRD)) {
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Return(UPRD(Arg3))
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}
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}
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} // End of switch(Arg2)
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} // End of if
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return (Buffer() {0x00})
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} // End of _DSM
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Device(PXSX)
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{
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Name(_ADR, 0x00000000)
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include ("PcieEpSel.asl")
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// NOTE: Any PCIE Hot-Plug dependency for this port is
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// specific to the CRB. Please modify the code based on
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// your platform requirements.
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Method(_PRW, 0) {
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//[-start-210617-STATHAM0002-modify]//
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#ifdef LCFC_SUPPORT
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Return(GPRW(0x69, 3)) // can wakeup from S3 state
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#else
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Return(GPRW(0x69, 4)) // can wakeup from S4 state
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#endif
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//[-end-210617-STATHAM0002-modify]//
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}
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}
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Method (_PS0, 0, Serialized)
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{
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If (CondRefOf (PPS0)) {
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PPS0 ()
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}
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}
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Method (_PS3, 0, Serialized)
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{
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If (CondRefOf (PPS3)) {
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PPS3 ()
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}
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}
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//
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// PCI_EXP_STS Handler for PCIE Root Port
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//
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Method(HPME,0,Serialized) {
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If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exists and has PME SCI Status set...
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Notify (PXSX, 0x2) //notify child device; this will cause its driver to clear PME_Status from device
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Store(1,PMSX) // clear rootport's PME SCI status
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Store(1,PSPX) // consume one pending PME notification to prevent it from blocking the queue
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}
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}
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