279 lines
9.0 KiB
Plaintext
279 lines
9.0 KiB
Plaintext
/**@file
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Serial IO UART Common ACPI definitions
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Register/SerialIoUartRegs.h>
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#define SERIAL_IO_UART_DISABLED 0
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#define SERIAL_IO_UART_PCI 1
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#define SERIAL_IO_UART_HIDDEN 2
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#define SERIAL_IO_UART_COM 3
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#define SERIAL_IO_UART_SKIP 4
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#define UART_PG_OFF 0
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#define UART_PG_ON 1
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#define UART_PG_AUTO 2
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Scope(\_SB.PC00) {
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//
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// Checks if UART specific DMA check _DSM is called
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//
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// @param[in] Arg0 UART mode
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//
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// @retval 1 if true, 0 otherwise
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//
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Method (UDSM, 1 ,Serialized) {
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If (LEqual(Arg0, ToUUID ("F7AF8347-A966-49FE-9022-7A9DEEEBDB27"))) {
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return (1)
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}
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return (0)
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}
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//
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// Uart DMA check _DSM
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//
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// @param[in] Arg0 Function Index
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// @param[in] Arg1 DMA/PIO support
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//
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// @retval case 0 Buffer with coresponding data
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// case 1 Integer [0:PIO; 1:DMA]
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// other Empty Buffer
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//
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Method (UDMA, 2, Serialized) {
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Switch (ToInteger(Arg0)) {
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Case (0) {
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Return (ToBuffer(0x3)) // Supports Function 1.
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}
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// Function 1, Return UART operating mode [0:PIO; 1:DMA]
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Case (1) {
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Return (ToInteger(Arg1))
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}
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} // End Switch statement
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Return (ToBuffer(0x0))
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}
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} //End Scope(\_SB.PC00)
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Scope(\_SB) {
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//
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// Uart Resources
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//
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Device (URSC) {
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Name (_HID, EISAID("PNP0C02"))
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Name (_STA, 0x3)
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Name (_UID, 5)
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//
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// Allocates remaining memory for Hidden/Com UART devices
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//
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// @param[in] Arg0 Mode
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// @param[in] Arg1 PciCfgBase
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//
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// @retval Resource buffer with memory ranges
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//
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Method (UARB, 2, Serialized) {
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If (LOr (LEqual (Arg0, SERIAL_IO_UART_HIDDEN), LEqual (Arg0, SERIAL_IO_UART_COM))) {
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OperationRegion (UACF, SystemMemory, Arg1, Add (R_SERIAL_IO_CFG_BAR0_LOW, 16))
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Field (UACF, AnyAcc, NoLock, Preserve) {
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Offset(R_SERIAL_IO_CFG_BAR0_LOW),
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BAR0, 64,
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BAR1, 64
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}
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Name (BUF1, ResourceTemplate () { Memory32Fixed (ReadWrite, 0, 0xFF8, BFR1) }) //4096 - 8 bytes, allocate remaining 4088 for BAR0 (MMIO BAR0)
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Name (BUF2, ResourceTemplate () { Memory32Fixed (ReadWrite, 0, 0x1000, BFR2) }) // allocate additional 4096 for BAR1 (PCI CFG SPACE)
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CreateDWordField (BUF1, BFR1._BAS, ADR1)
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CreateDWordField (BUF2, BFR2._BAS, ADR2)
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Store (And (BAR0, 0xFFFFFFFFFFFFF000), Local1)
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Store (Add (Local1, 8), ADR1) // Add 8 bytes to the address offset. First 8 bytes are allocated by the UAHx _CRS
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Store (And (BAR1, 0xFFFFFFFFFFFFF000), ADR2) // BAR1 (PCI CFG SPACE) Address
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ConcatenateResTemplate (BUF1, BUF2, Local0)
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Return (Local0)
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}
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Return (Buffer(){0x79, 0x00})
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}
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} // END Device(URSC)
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//
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// UART Hidden Resource allocation
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// Returns resource buffer with memory ranges used but not explicitely claimed by the device
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//
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// @param[in] Arg0 Pci Config Base
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// @param[in] Arg1 Interrupt number
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//
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// @retval Resource buffer with memory ranges
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//
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Method (UARH, 2, Serialized) {
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OperationRegion (UACF, SystemMemory, Arg0, Add(R_SERIAL_IO_CFG_BAR0_LOW, 8))
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Field (UACF, AnyAcc, NoLock, Preserve) {
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Offset (R_SERIAL_IO_CFG_BAR0_LOW),
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BAR0, 64
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}
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Name (BUF0, ResourceTemplate () { Memory32Fixed (ReadWrite, 0, 8, BFR0) }) // UAHx allocates only first 8 bytes
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Name (IBUF, ResourceTemplate () { Interrupt( ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {20}})
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CreateDWordField (BUF0, BFR0._BAS, ADR0)
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CreateDWordField (IBUF, SIRQ._INT, IRQN)
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Store (And (BAR0, 0xFFFFFFFFFFFFF000), Local0)
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Store (Local0, ADR0) // BAR0 first 8 bytes
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Store (Arg1, IRQN) // Interrupt Number
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ConcatenateResTemplate (BUF0, IBUF, Local1)
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Return (Local1)
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}
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//
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// Uart Power Gating Detection
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// - If UART is in PCI mode PG will be set to autonomous with _PS0/PS3 support
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// - Other modes:
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// If UART_PG_AUTO is applied function checks if LCR is programmed
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// Value different then 0 means that UART was used by the OS/SMM and PG should be OFF
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// If it is 0 PG is ON
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//
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// @param[in] Arg0 UART mode
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// @param[in] Arg1 UART PG mode
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// @param[in] Arg2 Pci Config Base
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//
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// @retval Final PG mode
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//
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Method (UAPG, 3, Serialized) {
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If (LNotEqual (Arg1, UART_PG_AUTO)) {
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Return (Arg1)
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}
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OperationRegion (UACF, SystemMemory, Arg2, Add (R_SERIAL_IO_CFG_BAR0_LOW, 8))
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Field (UACF, AnyAcc, NoLock, Preserve) {
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Offset(R_SERIAL_IO_CFG_BAR0_LOW),
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BAR0, 64
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}
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OperationRegion (UAB0, SystemMemory, And (BAR0, 0xFFFFFFFFFFFFF000), 0x10)
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Field (UAB0, ByteAcc, Lock, Preserve) {
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DLL, 8,
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DLH, 8,
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FCR, 8,
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LCR, 8
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}
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Store (LCR, Local0)
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If (LAnd (Local0, 0x7F)) {
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Return (UART_PG_OFF) // Disable D0 and D3 transitions
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}
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Return (UART_PG_ON) // Enable D0 and D3 transitions
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}
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//
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// Returns UART HID
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//
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// @param[in] Arg0 UART mode
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//
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// @retval HID value
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//
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Method (UHID, 1, Serialized) {
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If (LEqual (Arg0, SERIAL_IO_UART_COM)) { Return (EISAID("PNP0501")) }
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Return (EISAID("PNP0C02"))
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}
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//
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// Uart _PS3 handler
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//
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// @param[in] Arg0 UART PG mode
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// @param[in] Arg1 UART Pci Config Base
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//
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Method (UPS3, 2, Serialized) {
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If (LEqual (Arg0, UART_PG_ON)) {
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OperationRegion (UACF, SystemMemory, Arg1, Add (R_SERIAL_IO_CFG_PME_CTRL_STS, 4))
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Field (UACF, AnyAcc, NoLock, Preserve) {
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Offset(R_SERIAL_IO_CFG_BAR0_LOW),
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BAR0, 64
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}
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Field (UACF, ByteAcc, NoLock, Preserve) {
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Offset(R_SERIAL_IO_CFG_PME_CTRL_STS),
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PMEC, 8
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}
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OperationRegion (UAB0, SystemMemory, And (BAR0, 0xFFFFFFFFFFFFF000), Add (R_SERIAL_IO_MEM_PPR_RESETS_8BIT, 1))
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Field (UAB0, ByteAcc, NoLock, Preserve) {
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Offset (R_SERIAL_IO_MEM_PPR_RESETS_8BIT),
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PPRR, 8
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}
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Store (0x0, PPRR) // Place In reset state
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Store (0x3, PMEC)
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Or (PMEC, 0, PMEC) // perform a read to avoid ordering and noncoherency problems
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}
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//UART_PG_OFF - no action
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}
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//
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// Uart _PS0 handler
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//
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// @param[in] Arg0 UART PG mode
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// @param[in] Arg1 UART Pci Config Base
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//
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Method (UPS0, 2, Serialized) {
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If (LEqual (Arg0, UART_PG_ON)) {
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OperationRegion (UACF, SystemMemory, Arg1, Add (R_SERIAL_IO_CFG_PME_CTRL_STS, 4))
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Field (UACF, AnyAcc, NoLock, Preserve) {
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Offset(R_SERIAL_IO_CFG_BAR0_LOW),
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BAR0, 64
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}
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Field (UACF, ByteAcc, NoLock, Preserve) {
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Offset(R_SERIAL_IO_CFG_PME_CTRL_STS),
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PMEC, 8
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}
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Store (0x0, PMEC)
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Or (PMEC, 0, PMEC) // perform a read to avoid ordering and noncoherency problems
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OperationRegion (UAB0, SystemMemory, And (BAR0, 0xFFFFFFFFFFFFF000), Add (R_SERIAL_IO_MEM_PPR_RESETS_8BIT, 1))
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Field (UAB0, ByteAcc, NoLock, Preserve) {
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Offset (R_SERIAL_IO_MEM_PPR_RESETS_8BIT),
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PPRR, 8
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}
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Store(0x7, PPRR) // Out of reset
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}
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//UART_PG_OFF - no action
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}
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//
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// Uart _PSC handler
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//
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// @param[in] Arg0 UART Pci Config Base
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//
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Method (UPSC, 1, Serialized) {
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OperationRegion (UACF, SystemMemory, Add (Arg0, R_SERIAL_IO_CFG_PME_CTRL_STS), 4)
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Field (UACF, ByteAcc, NoLock, Preserve) {
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PMEC, 8
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}
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Return (And (PMEC, 0x3))
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}
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} //End Scope (\_SB)
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