226 lines
7.7 KiB
Plaintext
226 lines
7.7 KiB
Plaintext
/**@file
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Touch Host Controller ACPI
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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Name(_ADR, THC_ADR)
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Name(RSTL, 0) // Reset SW lock
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// _DSM - Device-Specific Method
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//
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// Arg0: UUID Unique function identifier
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// Arg1: Integer Revision Level - Will be 2 for HidSpi V1
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// Arg2: Integer Function Index (0 = Return Supported Functions)
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// Arg3: Package Parameters
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//
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Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
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If (PCIC(Arg0)) { Return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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If (LEqual (THC_MODE, 0x1)) {
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If(LEqual(Arg0,ToUUID("6E2AC436-0FCF-41AF-A265-B32A220DCFAB"))) {
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//
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// Switch on the function index
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//
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switch(ToInteger(Arg2)) {
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case(0) {
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// Switch on the revision level
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switch(ToInteger(Arg1)) {
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case (2) {
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// HidSpi v1 : Functions 0-6 inclusive are supported (0b01111111)
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Return (Buffer() {0x7F})
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}
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default {
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// Unsupported revision
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Return(Buffer() {0x00})
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}
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}
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} // End case0
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case(1) {
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ADBG ("THC THC_INPUT_REPORT_HEADER_ADDRESS")
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Return (ToInteger (THC_INPUT_REPORT_HEADER_ADDRESS))
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}
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case(2) {
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ADBG ("THC THC_INPUT_REPORT_BODY_ADDRESS")
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Return (ToInteger (THC_INPUT_REPORT_BODY_ADDRESS))
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}
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case(3) {
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ADBG ("THC THC_OUTPUT_REPORT_ADDRESS")
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Return (ToInteger (THC_OUTPUT_REPORT_ADDRESS))
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}
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case(4) {
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ADBG ("THC THC_READ_OPCODE")
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Name(BUF4, Buffer(1) {})
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Store(ToBuffer (THC_READ_OPCODE), Local0)
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Store(DerefOf(Index(Local0, 0)), Index(BUF4,0))
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Return (BUF4)
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}
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case(5) {
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ADBG ("THC THC_WRITE_OPCODE")
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Name(BUF5, Buffer(1) {})
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Store(ToBuffer (THC_WRITE_OPCODE), Local1)
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Store(DerefOf(Index(Local1, 0)), Index(BUF5,0))
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Return (BUF5)
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}
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case(6) {
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/*
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Bit 0-12: Reserved
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Bit 13: SPI Write Mode.
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0b0 - Writes are carried in single SPI mode
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0b1 - Writes are carried out in Multi-SPI mode as specified by bit 14-15
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Bit 14-15: Multi-SPI Mode
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0b00 - Single SPI Mode
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0b01 - Dual SPI Mode
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0b10 - Quad SPI Mode
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0b11 - Reserved
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*/
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ADBG ("THC THC_FLAGS")
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Return (ToInteger (THC_FLAGS))
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}
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default {
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// Unsupported function index
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Return (Buffer() {0})
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}
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} //EndSwitch
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//
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// No functions are supported for this UUID.
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//
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Return (Buffer() {0})
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} //EndIfUUID
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If(LEqual(Arg0,ToUUID("300D35B7-AC20-413E-8E9C-92E4DAFD0AFE"))) {
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switch(ToInteger(Arg2)) {
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case(0) {
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// Functions 1-3 inclusive are supported (0b00000111)
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Return (Buffer() {0x7})
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}
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case(1) {
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ADBG ("THC THC_CONNECTION_SPEED")
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/*
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Connection Speed in Hz
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Driver will round down to the nearest Spi frequency that THC supports.
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Max Speed is specific to each Soc design.
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*/
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Return (ToInteger (THC_CONNECTION_SPEED))
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}
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case(2) {
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ADBG ("THC THC_LIMIT_PACKET_SIZE")
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/*
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Bit 0: LimitPacketSize
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When set, limits SPI read & write packet size to 64B.
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Otherwise, THC uses Max Soc packet size for SPI Read and Write
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0 - Max Soc Packet Size
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1 - 64 Bytes
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Bit 1-31: Reserved
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*/
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Return (ToInteger (THC_LIMIT_PACKET_SIZE))
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}
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case(3) {
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ADBG ("THC THC_PERFORMANCE_LIMITATION")
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/*
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Bit 0-15: Performance Limitation
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Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation
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and begin of read operation. This value shall be in 10us multiples
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0 - Disabled
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1 - 65535 (0xFFFF) - up to 655350 us
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Bit 16-31: Reserved
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*/
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Return (ToInteger (THC_PERFORMANCE_LIMITATION))
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}
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default {
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// Unsupported function index
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Return (Buffer() {0})
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}
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} // End Switch
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} // End UUID
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} // End THC HID Mode
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If(LEqual(Arg0,ToUUID("84005682-5B71-41A4-8D66-8130F787A138"))) {
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switch(ToInteger(Arg2)) {
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case(0) {
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// Function 1/2 are supported (0b00000011)
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Return (Buffer() {0x3})
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}
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case(1) {
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ADBG ("THC THC_ACTIVE_LTR")
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Return (ToInteger (THC_ACTIVE_LTR))
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}
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case(2) {
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ADBG ("THC THC_IDLE_LTR")
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Return (ToInteger (THC_IDLE_LTR))
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}
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default {
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// Unsupported function index
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Return (Buffer() {0})
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}
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} // End Switch
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} // End UUID
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Return(Buffer(){})
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} // End _DSM
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If (LNotEqual (THC_WAKE_INT, 0)) {
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Name (_S0W, 3)
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}
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//
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// Expose THC Resources only when THC Wake is enabled
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//
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If (LNotEqual (THC_WAKE_INT, 0)) {
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Method(_CRS, 0x0, Serialized) {
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Return (TINT (THC_WAKE_INT))
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}
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}
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If (LEqual (THC_MODE, 0x1)) {
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Method(_INI) {
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ADBG ("THC _INI")
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// configure gpio pad in gpio driver mode
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SHPO(THC_RST_PAD, 1)
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// Make sure both pads are in GPIO mode
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SPMV(THC_RST_PAD, 0)
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// Put device in inital reset state
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SPC0(THC_RST_PAD, Or (0x42000200, And(Not(And(THC_RST_TRIGGER,1)),1)))
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}
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Method (_RST, 0, Serialized) {
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ADBG ("THC _RST")
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// Wait until Lock is freed
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// Note: Lock should be not required because Method is serialized
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// added to avoid race conditions
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While(LEqual(RSTL, 1)) {
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Sleep (10)
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}
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// Acquire Lock
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Store (1, RSTL)
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SGOV(THC_RST_PAD, And(THC_RST_TRIGGER,1))
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Sleep (300)
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SGOV(THC_RST_PAD, And(Not(And(THC_RST_TRIGGER,1)), 1))
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// Release Lock
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Store (0, RSTL)
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}
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}
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