126 lines
3.7 KiB
Plaintext
126 lines
3.7 KiB
Plaintext
/** @file
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ACPI Support for PCIe SSD
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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// Include PciEpSel.asl for PCIe SSD support
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// Input parameters:
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OperationRegion(PCCX,PCI_Config,0x0,16) // PCI Config Space Class Code
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Field(PCCX, ByteAcc, NoLock, Preserve) {
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DVID, 32, // Vendor&Device ID,
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Offset(9),
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PIXX, 8, // Programming Interface
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SCCX, 8, // Sub Class Code
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BCCX, 8, // Base Class Code
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}
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Method(PAHC, Zero, Serialized) // Check if PCIe AHCI Controller
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{
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If(LEqual(BCCX, 0x01)){ // Check Sub Class Code and Base Class Code
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If(LEqual(SCCX, 0x06)){
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If(LEqual(PIXX, 0x01)){
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Return(0x01)
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}
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}
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}
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Return(0x00)
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}
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Method(PNVM, Zero, Serialized) // Check if PCIe NVMe
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{
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If(LEqual(BCCX, 0x01)){ // Check Sub Class Code and Base Class Code
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If(LEqual(SCCX, 0x08)){
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If(LEqual(PIXX, 0x02)){
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Return(0x01)
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}
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}
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}
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Return(0x00)
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}
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//
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// Check if EP(End Point) is present.
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// Arguments: (0)
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// Return: EP presence status
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// 0->EP is absent; 1->EP is present
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//
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Method(PRES, Zero, Serialized) {
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If(LEqual (DVID, 0xFFFFFFFF)) {
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Return(0)
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} Else {
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Return(1)
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}
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}
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//
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// Check if EP (End Point) is GFX.
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// Arguments: (0)
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// Return:
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// 0->EP is not Gfx; 1->EP is GFX
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//
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Method (ISGX, Zero, Serialized) // Check if PCIe GFX device
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{
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If (LEqual (BCCX, 0x03)){ // Check Base Class Code
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Return (0x01)
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}
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Return (0x00)
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}
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If (CondRefOf (\STD3)) {
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If (LNotEqual (\STD3, 0)) {
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Method (_DSD, 0)
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{
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If (LOr (PAHC (), PNVM ())) {
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Return (
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Package () {
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ToUUID ("5025030F-842F-4AB4-A561-99A5189762D0"),
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// Enable D3 Support for NVMe Storage
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Package () {
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Package (2) {"StorageD3Enable", 1} // 1 - Enable; 0 - Disable
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}
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}
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)
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} Else {
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Return (
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Package () {
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ToUUID ("5025030F-842F-4AB4-A561-99A5189762D0"),
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Package () {
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Package (2) {"StorageD3Enable", 0} // 1 - Enable; 0 - Disable
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}
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}
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)
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}
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}
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}
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}
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