461 lines
13 KiB
Plaintext
461 lines
13 KiB
Plaintext
/**@file
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@copyright
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INTEL CONFIDENTIAL
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Copyright (c) 2015 - 2021 Intel Corporation. All rights reserved
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This software and associated documentation (if any) is furnished
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under a license and may only be used or copied in accordance
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with the terms of the license. Except as permitted by the
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license, no part of this software or documentation may be
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reproduced, stored in a retrieval system, or transmitted in any
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form or by any means without the express written consent of
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Intel Corporation.
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This file contains an 'Intel Peripheral Driver' and is uniquely
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identified as "Intel Reference Module" and is licensed for Intel
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CPUs and chipsets under the terms of your license agreement with
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Intel or your vendor. This file may be modified by the user, subject
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to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#define MODPHY_PG_TIMEOUT_IN_MS 10000
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External(SIME)
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//
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// HSIO Library
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Scope(\_SB) {
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//
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// PCIe root port modPHY power gating enable
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// Arg0 - Index of PCIe root port(1 - based)
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//
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Method(PSD3, 1, Serialized) {
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Store(0, Local0) //Time check counter variable
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If (LOr (LEqual (SIME, 1), LNot(IMPS()))) {
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Return ()
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}
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Switch(Add(MODPHY_SPD_GATING_PCIE_RP1, Decrement(Arg0))) {
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Case (MODPHY_SPD_GATING_PCIE_RP1) {
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Store(1, RAA0)
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While (LAnd(Lequal(APA0, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP2) {
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Store(1, RAA1)
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While (LAnd(Lequal(APA1, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP3) {
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Store(1, RAA2)
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While (LAnd(Lequal(APA2, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP4) {
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Store(1, RAA3)
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While (LAnd(Lequal(APA3, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP5) {
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Store(1, RPB0)
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While (LAnd(Lequal(APB0, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP6) {
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Store(1, RPB1)
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While (LAnd(Lequal(APB1, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP7) {
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Store(1, RPB2)
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While (LAnd(Lequal(APB2, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP8) {
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Store(1, RPB3)
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While (LAnd(Lequal(APB3, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP9) {
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Store(1, RPC0)
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While (LAnd(Lequal(APC0, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP10) {
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Store(1, RPC1)
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While (LAnd(Lequal(APC1, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP11) {
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Store(1, RPC2)
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While (LAnd(Lequal(APC2, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP12) {
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Store(1, RPC3)
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While (LAnd(Lequal(APC3, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP13) {
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Store(1, RPD0)
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While (LAnd(Lequal(APD0, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP14) {
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Store(1, RPD1)
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While (LAnd(Lequal(APD1, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP15) {
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Store(1, RPD2)
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While (LAnd(Lequal(APD2, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP16) {
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Store(1, RPD3)
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While (LAnd(Lequal(APD3, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP17) {
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Store(1, RPE0)
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While (LAnd(Lequal(APE0, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP18) {
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Store(1, RPE1)
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While (LAnd(Lequal(APE1, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP19) {
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Store(1, RPE2)
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While (LAnd(Lequal(APE2, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP20) {
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Store(1, RPE3)
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While (LAnd(Lequal(APE3, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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}
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If(LGreaterEqual(Local0, MODPHY_PG_TIMEOUT_IN_MS)) {
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ADBG("Error: Timeout occurred")
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}
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}
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//
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// PCIe root port modPHY power gating disable
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// Arg0 - Index of PCIe root port(1 - based)
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//
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Method(PSD0, 1, Serialized) {
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Store(0, Local0) //Time check counter variable
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If (LOr (LEqual (SIME, 1), LNot(IMPS()))) {
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Return ()
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}
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Switch(Add(MODPHY_SPD_GATING_PCIE_RP1, Decrement(Arg0))) {
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Case (MODPHY_SPD_GATING_PCIE_RP1) {
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Store(0, RAA0)
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While (LAnd(Lequal(APA0, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP2) {
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Store(0, RAA1)
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While (LAnd(Lequal(APA1, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP3) {
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Store(0, RAA2)
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While (LAnd(Lequal(APA2, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP4) {
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Store(0, RAA3)
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While (LAnd(Lequal(APA3, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP5) {
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Store(0, RPB0)
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While (LAnd(Lequal(APB0, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP6) {
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Store(0, RPB1)
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While (LAnd(Lequal(APB1, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP7) {
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Store(0, RPB2)
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While (LAnd(Lequal(APB2, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP8) {
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Store(0, RPB3)
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While (LAnd(Lequal(APB3, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP9) {
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Store(0, RPC0)
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While (LAnd(Lequal(APC0, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP10) {
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Store(0, RPC1)
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While (LAnd(Lequal(APC1, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP11) {
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Store(0, RPC2)
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While (LAnd(Lequal(APC2, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP12) {
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Store(0, RPC3)
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While (LAnd(Lequal(APC3, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP13) {
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Store(0, RPD0)
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While (LAnd(Lequal(APD0, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP14) {
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Store(0, RPD1)
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While (LAnd(Lequal(APD1, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP15) {
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Store(0, RPD2)
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While (LAnd(Lequal(APD2, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP16) {
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Store(0, RPD3)
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While (LAnd(Lequal(APD3, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP17) {
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Store(0, RPE0)
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While (LAnd(Lequal(APE0, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP18) {
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Store(0, RPE1)
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While (LAnd(Lequal(APE1, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP19) {
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Store(0, RPE2)
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While (LAnd(Lequal(APE2, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_PCIE_RP20) {
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Store(0, RPE3)
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While (LAnd(Lequal(APE3, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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}
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If(LGreaterEqual(Local0, MODPHY_PG_TIMEOUT_IN_MS)) {
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ADBG("Error: Timeout occurred")
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}
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}
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//
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//Controller SPD D3 Method
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//
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// This method sets the appropriate R_CNL_PCH_PWRM_MODPHY_PM_CFG5[MSPDRTREQ],
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// Setting the MSPDRTREQ bit for a controller implies that ASL code provides consent for
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// SPD to be gated for the corresponding controller's lanes (PMC will gate SPD for the
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// corresponding controller's lanes).
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//
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// Arg0 - PCH Controller ENUM
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//
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Method(CSD3, 1, Serialized) {
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Store(0, Local0) //Time check counter variable
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If (LOr (LEqual (SIME, 1), LNot(IMPS()))) {
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Return ()
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}
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Switch (ToInteger(arg0)) {
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Case (MODPHY_SPD_GATING_SATA) {
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Store(1, RSAT)
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While (LAnd(Lequal(ASAT, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_GBE) {
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Store(1, RGBE)
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While (LAnd(Lequal(AGBE, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_XHCI) {
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Store(1, RXHC)
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While (LAnd(Lequal(AXHC, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_XDCI) {
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Store(1, RXDC)
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While (LAnd(Lequal(AXDC, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_UFS) {
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Store(1, RUFS)
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While (LAnd(Lequal(AUFS, 0), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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}
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If(LGreaterEqual(Local0, MODPHY_PG_TIMEOUT_IN_MS)) {
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ADBG("Error: Timeout occurred")
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}
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}
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//
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// Controller SPD D0 Method
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//
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// This method clears the appropriate R_CNL_PCH_PWRM_MODPHY_PM_CFG5[MSPDRTREQ],
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// Clearing the MSPDRTREQ bit for a controller implies that ASL code does not provide
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// consent for SPD to be gated for the corresponding controller's lanes (PMC will "un-gate"
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// SPD for the corresponding controller's lanes).
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//
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// Arg0 - PCH Controller ENUM
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//
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Method(CSD0, 1, Serialized) {
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Store(0, Local0) //Time check counter variable
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If (LOr (LEqual (SIME, 1), LNot(IMPS()))) {
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Return ()
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}
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Switch (ToInteger(arg0)) {
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Case (MODPHY_SPD_GATING_SATA) {
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Store(0, RSAT)
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While (LAnd(Lequal(ASAT, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_GBE) {
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Store(0, RGBE)
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While (LAnd(Lequal(AGBE, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_XHCI) {
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Store(0, RXHC)
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While (LAnd(Lequal(AXHC, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_XDCI) {
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Store(0, RXDC)
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While (LAnd(Lequal(AXDC, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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Case (MODPHY_SPD_GATING_UFS) {
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Store(0, RUFS)
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While (LAnd(Lequal(AUFS, 1), LLess(Local0, MODPHY_PG_TIMEOUT_IN_MS))) {
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Increment(Local0)
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Sleep(1)
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}
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}
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}
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If(LGreaterEqual(Local0, MODPHY_PG_TIMEOUT_IN_MS)) {
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ADBG("Error: Timeout occurred")
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}
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}
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}
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