494 lines
15 KiB
Plaintext
494 lines
15 KiB
Plaintext
/**@file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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//
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// Since asl compiler update to 2018 version
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// Empty template will casuse warrning
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// using this Macro to replace empty ResourceTemplate with End Tag
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//
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#ifndef EMPTY_RESOURCE_TEMPLATE
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#define EMPTY_RESOURCE_TEMPLATE Buffer(){0x79, 0x00}
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#endif
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#include <Library/PchInfoLib.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/PchPcieRpRegs.h>
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#include <Register/PmcRegs.h>
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#include <PcieRpMacroDefinition.h>
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#define PCR_MMIO_SIZE_PER_PID 0x10000 ///< 64KB
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#define PCR_MMIO_SIZE 0x01000000 ///< 16MB
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#define PCR_MMIO_SIZE_EX 0x10000000 ///< 256MB, used by SBREG_BAR 20-bit address platforms
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Name (PNVB, 0xFFFF0000) // PCH NVS Base address
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Name (PNVL, 0xAA55) // PCH NVS Length
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Include ("PchNvs.asl")
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//
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// Include GPIO macros and access library
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//
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Include("HsioDefine.asl")
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Include("GpioAcpiDefines.h")
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Include("HsioLib.asl")
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//
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// Trace Hub debug library
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// Include it earlier so the debug function can be used as soon as possible
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//
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Include ("TraceHubDebug.asl")
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Name(PCHH,PCH_H) // PCH H
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Name(PCHN,PCH_N) // PCH N
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Name(PCHL,PCH_LP) // PCH LP
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Name(PCHP,PCH_P) // PCH P
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Name(PCHM,PCH_M) // PCH M
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Name(PCHX,PCH_S) // PCH S
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//
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// PME event (PCH's GPE 6Dh) is received when any PCH internal device with
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// PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal.
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// Dedicated _L6D method is not needed if its only purpose is to notify the device.
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// Instead to properly handle this GPE event below requirements need to be fulfilled
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// - _PRW for GPE 6Dh in devices capable of generating PME (XHCI, XDCI, GbE, HDA)
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// - _S0W(3) and _DSW is present within those devices
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Scope (\_SB) {
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//
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// PCH RC _WAK handler
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// This method should be called from _WAK function
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// to perform necessary PCH actions upon wake
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//
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Method(PWAK, 1) {
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//
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// Arg0 - sleeping state (1 for S1, 2 for S2, etc.)
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//
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//
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// On S3 resume call S0i2/3 wake handler
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//
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If (LEqual (Arg0, 3)) {
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S23W()
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}
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}
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//
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// PCH S0i2/3 dynamic switching
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//
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// 0: Device inactive
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// 1: Device active
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// 2: Device statically disabled
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//
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Name (HDAA, 1) // HD Audio Active state flag
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Name (DISA, 1) // Display Active state flag
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Name (CIWF, 1) // CNVi WiFi Active state flag
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Name (CIBT, 1) // CNVi BT Active state flag
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Name (S23C, 0) // Flag indicating if function was called and static disabling was taken into account
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//
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// This method should be called upon resume from S3 state
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// from _WAK method to reinitialize device state variables
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// that impact S0i2/S0i3 flow
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//
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Method(S23W, 0) {
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//
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// Upon wake from S3 reinitialize state variables to default
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// which is also safe config and one that is left after BIOS boot
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//
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Store (1, HDAA)
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Store (1, DISA)
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Store (1, CIWF)
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Store (1, CIBT)
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}
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//
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// Display ON event handler for S0i2/3 dynamic switching
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// To be called in 'GUAM - Global User Absent Mode' or similar screen/display on event handler
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//
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Method(DION, 0) {
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S023(1, 1) // CS Exit event - Display state ON
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}
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//
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// Display OFF event handler for S0i2/3 dynamic switching
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// To be called in 'GUAM - Global User Absent Mode' or similar screen/display off event handler
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//
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Method(DIOF, 0) {
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S023(1, 0) // CS Entry event - Display state OFF
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}
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//
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// S0i2/3 dynamic switching
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// Arg0 - Caller: 0 - HD Audio, 1 - Display, 2 - CNVi-WiFi, 3 - CNVi-BT
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// Arg1 - Device state: 0 - inactive, 1 - active
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//
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Method(S023, 2, Serialized) {
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}
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//
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// PCH reserved resources
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//
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Device(PRRE) {
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Name(_HID,EISAID("PNP0C02")) // motherboard resource
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Name(_UID,"PCHRESV")
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Name(_STA,0x8) // device present and decodes its resources, but not to be displayed in OSPM
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Method(_CRS,0,Serialized)
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{
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Name(BUF0,ResourceTemplate(){
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//
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// PCH RESERVED MMIO RANGE
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// Refer to PchReservedResources.h for ranges used by PCH
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//
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// skip over address range that might be claimed by the Intel Serial IO, and TraceHub
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// The SerialIO ranges will be handled by SIRC device.
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// skip 0xFC800000 - 0xFCFFFFFF for PCH Trace Hub : SW BAR space
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// skip 0xFD800000 - 0xFDFFFFFF for PCH Trace Hub : SW BAR space (ADL)
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Memory32Fixed (ReadWrite, 0xFE000000, 0x00020000) // 0xFE000000 - 0xFE01FFFF
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// Skip 0xFE020000 - 0xFE04BFFF for Serial IO
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Memory32Fixed (ReadWrite, 0xFE04C000, 0x00004000) // 0xFE04C000 - 0xFE04FFFF
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Memory32Fixed (ReadWrite, 0xFE050000, 0x00060000) // 0xFE050000 - 0xFE0AFFFF
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// Skip 0xFE0B0000 - 0xFE0CFFFF for eSPI
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Memory32Fixed (ReadWrite, 0xFE0D0000, 0x00030000) // 0xFE0D0000 - 0xFE0FFFFF
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// skip 0xFE100000 - 0xFE1FFFFF for PCH Trace Hub : MTB BAR space
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Memory32Fixed (ReadWrite, 0xFE200000, 0x00600000) // 0xFE200000 - 0xFE7FFFFF
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// BIOS decoding range. Assume it's always 16MB.
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Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000)
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// ACPI Base
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IO (Decode16,0,0,0x1,0xFF,ABAR)
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})
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// Update ACPI IO region
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CreateWordField (BUF0, ABAR._MIN,AMIN)
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CreateWordField (BUF0, ABAR._MAX,AMAX)
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Store (PMBS, AMIN)
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Store (PMBS, AMAX)
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//
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// Claim SBREG_MMIO range except for some GPIO communities which are used by GPIO OS driver, refer to Gpio.asl
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//
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// PID_GPIOCOM0 = 0x6E
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// PID_GPIOCOM1 = 0x6D
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// PID_GPIOCOM2 = 0x6C
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// PID_GPIOCOM3 = 0x6B
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// PID_GPIOCOM4 = 0x6A
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// PID_GPIOCOM5 = 0x69
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//
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// claim region from SBREG_BASE to first GPIO community claimed by GPIO driver.
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//
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Name(SBR0, ResourceTemplate(){ Memory32Fixed (ReadWrite, 0x0, PCH_GPIO_COM5, SBRR) })
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CreateDWordField (SBR0, SBRR._BAS, BAS0)
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Store (SBRG, BAS0)
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ConcatenateResTemplate(BUF0, SBR0, Local0)
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//
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// claim GPIO communities that GPIO driver does not use.
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//
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If (LOr (LEqual (PCHS, PCHH), LEqual (PCHS, PCH_S))) {
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//
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// claim GPIO COM2
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//
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Name (SBRS, ResourceTemplate () {Memory32Fixed (ReadWrite, 0x0, 0x0, SBSA) }) // Community 2
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CreateDWordField (SBRS, SBSA._BAS, BAS1)
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CreateDWordField (SBRS, SBSA._LEN, LEN1)
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Store (Add (SBRG, PCH_GPIO_COM2), BAS1)
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Store (PCR_MMIO_SIZE_PER_PID, LEN1)
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ConcatenateResTemplate (Local0, SBRS, Local1)
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} Else {
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//
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// claim GPIO COM2 & COM3
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//
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Name (SBRL, ResourceTemplate () {Memory32Fixed (ReadWrite, 0x0, 0x0, SBSB) }) // Community 2, 3
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CreateDWordField (SBRL, SBSB._BAS, BAS2)
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CreateDWordField (SBRL, SBSB._LEN, LEN2)
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Store(Add (SBRG, PCH_GPIO_COM3), BAS2)
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Store(Multiply (PCR_MMIO_SIZE_PER_PID, 2), LEN2)
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ConcatenateResTemplate(Local0, SBRL, Local1)
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}
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//
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// claim the rest of SBREG range, from above GPIO COM0 to SBREG range upper limit
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//
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Name (SBRE, ResourceTemplate () {Memory32Fixed (ReadWrite, 0x0, 0x0, SEND) })
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CreateDWordField (SBRE, SEND._BAS, BAS3)
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CreateDWordField (SBRE, SEND._LEN, LEN3)
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Store (Add (SBRG, Add (PCH_GPIO_COM0, PCR_MMIO_SIZE_PER_PID)), BAS3)
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If (LEqual (PCHS, PCH_S)) {
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Store (Subtract (Add (SBRG, PCR_MMIO_SIZE_EX), BAS3), LEN3)
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} Else {
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Store (Subtract (Add (SBRG, PCR_MMIO_SIZE), BAS3), LEN3)
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}
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ConcatenateResTemplate (Local1, SBRE, Local2)
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return (Local2)
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} // Method (_CRS)
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} // Device (PRRE)
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Device(IOTR) {
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//
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// This device claims IO range reserved for IO traps
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// to prevent OS from reusing it for other purposes
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//
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Name(_HID,EISAID("PNP0C02"))
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Name(_UID,"IoTraps")
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Method(_CRS) {
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Name(BUF0,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG0) })
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Name(BUF1,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG1) })
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Name(BUF2,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG2) })
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Name(BUF3,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG3) })
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CreateWordField(BUF0,TAG0._MIN,AMI0);CreateWordField(BUF0,TAG0._MAX,AMA0)
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CreateWordField(BUF1,TAG1._MIN,AMI1);CreateWordField(BUF1,TAG1._MAX,AMA1)
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CreateWordField(BUF2,TAG2._MIN,AMI2);CreateWordField(BUF2,TAG2._MAX,AMA2)
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CreateWordField(BUF3,TAG3._MIN,AMI3);CreateWordField(BUF3,TAG3._MAX,AMA3)
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Store(0, Local2)
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//
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// Win7 can't store result of ConcatenateResTemplate directly into one of its input parameters
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// When ITS0, ITS1, ITS2 and ITS3 is 1. Update BUF0, BUF1, BUF2 and BUF3 then store to Local0
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//
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If(LEqual(ITS0,1)) {
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Store(ITA0,AMI0)
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Store(ITA0,AMA0)
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Store(BUF0, Local0)
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Store(1, Local2)
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}
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If(LEqual(ITS1,1)) {
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Store(ITA1,AMI1)
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Store(ITA1,AMA1)
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If (LEqual (Local2,1)){
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ConcatenateResTemplate(BUF1, Local0, Local1)
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Store(Local1, Local0)
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} Else {
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Store(BUF1, Local0)
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Store(1, Local2)
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}
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}
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If(LEqual(ITS2,1)) {
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Store(ITA2,AMI2)
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Store(ITA2,AMA2)
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If (LEqual(Local2, 1)){
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ConcatenateResTemplate(BUF2, Local0, Local1)
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Store(Local1, Local0)
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} Else {
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Store(BUF2, Local0)
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Store(1, Local2)
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}
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}
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If(LEqual(ITS3,1)) {
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Store(ITA3,AMI3)
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Store(ITA3,AMA3)
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If(LEqual(Local2, 1)){
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ConcatenateResTemplate(BUF3, Local0, Local1)
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Store(Local1, Local0)
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} Else {
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Store(BUF3, Local0)
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Store(1, Local2)
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}
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}
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If(LEqual(Local2, 1)){
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Return(Local0)
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} Else {
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Return(EMPTY_RESOURCE_TEMPLATE)
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}
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}
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}
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}
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Scope (\_SB.PC00) {
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Name(TEMP,0) // scratch variable that does not cause compiler warnings as writes to Localx variables do.
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//
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// LPC Bridge - Device 31, Function 0, this is only for PCH register Memory Region declare,
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// it's better to be declared as early as possible since it's widely used in whole ACPI name space.
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// Please add any code which needs to reference any register of it after this
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//
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Device(LPCB) {
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Name(_ADR, 0x001F0000)
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Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})}
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OperationRegion(LPC, PCI_Config, 0x00, 0x100)
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Field(LPC, AnyAcc, NoLock, Preserve)
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{
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Offset(0x02),
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CDID, 16,
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Offset(0x08),
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CRID, 8,
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Offset(R_LPC_CFG_IOD), // 0x80
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IOD0, 8,
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IOD1, 8,
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Offset(0xA0),
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, 9,
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PRBL, 1,
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Offset(R_LPC_CFG_BC), // 0xDC
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, 2,
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ESPI, 1,
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}
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}
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//
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// SMBus Controller - Device 31, Function 4
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//
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Device(SBUS) {
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Name(_ADR,0x001F0004)
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Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})}
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}
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}
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Include("Pmc.asl")
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Scope (\_SB.PC00) {
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Name(LTEN, 0)
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Name(LMSL, 0)
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Name(LNSL, 0)
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} //scope
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If (LNotEqual(GBES,0)) {
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//
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// LAN Controller
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//
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Scope (\_SB.PC00) {
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Device(GLAN) { // GbE Controller
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Name(_ADR, 0x001F0006)
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Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})}
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Name(_S0W, 3) // Device can wake itself from D3 in S0
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Method(_PRW, 0) {
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//[-start-210617-STATHAM0002-modify]//
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#ifdef LCFC_SUPPORT
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Return(GPRW(0x6D, 3)) // can wakeup from S3 state
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#else
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Return(GPRW(0x6D, 4)) // can wakeup from S4 state
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#endif
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//[-end-210617-STATHAM0002-modify]//
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}
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//
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// Define a Memory Region that will allow access to the GLAN PCI Configuration Space
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//
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OperationRegion(LANR, PCI_Config, 0x00, 0x100)
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Field(LANR,ByteAcc,NoLock,Preserve) {
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DVID, 16,
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Offset(0xCC), // R_GBE_CFG_PMCS Power management control and status PMCS_DR
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,8,
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PMEE,1,
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,6,
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PMES,1
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}
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Method(GPEH) {
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If(LEqual(^DVID,0xFFFF)) {
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Return
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}
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If(LEqual(PMES,1)) {
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Notify(\_SB.PC00.GLAN, 0x02)
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}
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}
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Method(_DSW, 3) {}
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} // end "GbE Controller"
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} //scope
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}
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//
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// xHCI Controller - Device 20, Function 0
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//
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Include("PchXhci.asl")
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//
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// xDCI (OTG) Controller - Device 20, Function 1
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//
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include("PchXdci.asl")
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Scope(\_SB_.PC00) {
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//
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// High Definition Audio Controller - Device 31, Function 3
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//
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include("PchHda.asl")
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//
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// High Definition Audio - SoundWire Controller
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//
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include("PchHdaSoundWireCtrl.asl")
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If (LNotEqual(UAOE,0)) {
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//
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// High Definition Audio - USB Audio Offload
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//
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include("PchHdaUsbAudioOffload.asl")
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}
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//
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// High Definition Audio - Intel Display Audio
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//
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include("PchHdaIntelDisplayAudio.asl")
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}
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Include ("PchFru.asl")
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//
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// Integrated Sensor Hub definition
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//
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Include ("PchIsh.asl")
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//
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// MEI 1 definition
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//
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Include ("PchHeci.asl")
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Include ("PchTraceHub.asl")
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#if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
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//
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// Timed GPIO
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//
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Include ("TimedGpio.asl")
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//
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// GBE TSN
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//
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Include ("PchTsn.asl")
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#endif
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//[start-210915-STORM1113-modify]
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//[-start-210916-QINGLIN0067-modify]//
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#if defined(C770_SUPPORT) || defined(S370_SUPPORT)
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//[-end-210916-QINGLIN0067-modify]//
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// 1 based, card reader RP 10
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Scope( \_SB.PC00.RP10.PXSX ) {
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Name (_S0W, 3)
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}
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#endif
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//[end-210915-STORM1113-modify]
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