336 lines
16 KiB
Plaintext
336 lines
16 KiB
Plaintext
/**@file
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SoundWire Controllers ACPI
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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// Values for XTAL 24MHz
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#define V_HDA_SNDW_IP_CLOCK_XTAL24MHZ 24000000 // 24 MHz
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#define V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL24MHZ 6000000 // 6 MHz
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#define V_HDA_SNDW_FRAME_ROW_SIZE_XTAL24MHZ 125
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#define V_HDA_SNDW_FRAME_COL_SIZE_XTAL24MHZ 2
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// Values for XTAL 38.4MHz
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#define V_HDA_SNDW_IP_CLOCK_XTAL38P4MHZ 38400000 // 38.4 MHz
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#define V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL38P4MHZ 4800000 // 4.8 MHz
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#define V_HDA_SNDW_FRAME_ROW_SIZE_XTAL38P4MHZ 50
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#define V_HDA_SNDW_FRAME_COL_SIZE_XTAL38P4MHZ 4
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// Values for XTAL 19.2MHz
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#define V_HDA_SNDW_IP_CLOCK_XTAL19P2MHZ 19200000 // 19.2 MHz
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#define V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL19P2MHZ 4800000 // 4.8 MHz
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#define V_HDA_SNDW_FRAME_ROW_SIZE_XTAL19P2MHZ 50
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#define V_HDA_SNDW_FRAME_COL_SIZE_XTAL19P2MHZ 4
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#define V_HDA_SNDW_SW_INTERFACE_REVISION 0x00010000
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#define SDW_INTEL_QUIRK_MSK_INDEX 0
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#define SDW_INTEL_IP_CLK_INDEX 1
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#define SDW_INTEL_DATA_ON_ACTIVE_INTERVAL_SELECT_INDEX 2
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#define SDW_INTEL_DATA_ON_DELAY_SELECT 3
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#define SDW_INTEL_AUTONOMOUS_CLK_STOP_INDEX 4
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#define SDW_MIPI_CLK_STOP_MODE0_SUPPORT_INDEX 5
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#define SDW_MIPI_CLK_STOP_MODE1_SUPPORT_INDEX 6
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#define SDW_MIPI_CLK_FREQ_SUPPORTED_INDEX 7
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#define SDW_MIPI_DEFAULT_FRAME_RATE_INDEX 8
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#define SDW_MIPI_DEFAULT_FRAME_ROW_SIZE_INDEX 9
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#define SDW_MIPI_DEFAULT_FRAME_COL_SIZE_INDEX 10
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#define SDW_MIPI_DYNAMIC_FRAME_SHAPE_INDEX 11
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#define SDW_MIPI_CMD_ERROR_THRESHOLD_INDEX 12
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#define SDW_LNK_DESC_GUID_INDEX 0
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#define SDW_LNK_DESC_DATA_INDEX 1
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#define SDW_LNK_DESC_DATA(LinkDesc) DeRefOf(Index(LinkDesc, SDW_LNK_DESC_DATA_INDEX))
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#define SDW_LNK_ENTRY(LinkDesc, EntryIndex) DeRefOf(Index(SDW_LNK_DESC_DATA(LinkDesc), EntryIndex))
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#define SDW_LNK_ENTRY_DATA(LinkDesc, EntryIndex) Index (SDW_LNK_ENTRY(LinkDesc, EntryIndex), 1)
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//
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// SoundWire Link Controllers definition (up to 4 controllers can be defined)
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//
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Scope(HDAS)
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{
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//
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// Address (_ADR) encoding:
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// Bits 28-31 - Link Type
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// 0 = HD-Audio, 1 = DSP, 2 = PDM, 3 = SSP, 4 = SoundWire
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// Bits 0-3 - Device Instance ID (unique to virtual bus).
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// SoundWire:
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// 0-3 = Bus Instance 0 - 3
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// For example:
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// 1) SWC0: _ADR(0x10000000) - LinkType[31:28] = 1 (DSP), Instance[3:0] = 0
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// 2) SWC1: _ADR(0x40000001) - LinkType[31:28] = 4 (SW), Instance[3:0] = 1
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// 3) SWC2: _ADR(0x40000002) - LinkType[31:28] = 4 (SW), Instance[3:0] = 2
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//
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//
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// SoundWire Link Controller (Aggregated defintion for all 4 contoller instances - LinkType = SoundWire)
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//
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Device(SNDW) {
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Name(_ADR, 0x40000000)
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Name(_CID, Package() {
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// Precedence order does matter for evaluation of list
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"PRP00001", // to indicate that we want to use DeviceTree-like "compatible" matching, Linux only
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"PNP0A05" // generic container device always placed last, makes sure entry is ignored by Windows with no yellow bangs if there is no matching driver
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})
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Method(_STA, 0, NotSerialized) { // _STA: Status
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Return (0x0B)
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}
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//
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// Update Quirk mask based on enabled SoundWire interfaces and update autonomous clock stop based on PchPolicy
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// Arg0 - Link instance (LNK[N])
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// Arg1 - SoundWire Quirk Mask
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// Arg2 - Autonomous Clock Stop
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Method(QCFG, 3, NotSerialized) {
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// Update LNK[N] object, "intel-quirk-mask" property value
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// in accordance with SoundWire Link [N] enable/disable state in PchPolicy
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Store (Arg1, SDW_LNK_ENTRY_DATA(Arg0, SDW_INTEL_QUIRK_MSK_INDEX))
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// Update LNK[N] object, "intel-autonomous-clock-stop" property value
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// in accordance with SoundWire Link [N] Autonomous Clock Stop enable/disable state in PchPolicy
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Store (Arg2, SDW_LNK_ENTRY_DATA(Arg0, SDW_INTEL_AUTONOMOUS_CLK_STOP_INDEX))
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}
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//
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// Update Link properties (Clock, Supported frequency, Frame) based on selected XTAL
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// Arg0 - Link instance (LNK[N])
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// Arg1 - XTAL
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//
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Method(XCFG, 2, NotSerialized) {
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If (Arg1 == 24000000) {
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Store (V_HDA_SNDW_IP_CLOCK_XTAL24MHZ, Local0)
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Store (V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL24MHZ, Local1)
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Store (V_HDA_SNDW_FRAME_ROW_SIZE_XTAL24MHZ, Local2)
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Store (V_HDA_SNDW_FRAME_COL_SIZE_XTAL24MHZ, Local3)
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}
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ElseIf (Arg1 == 38400000) {
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Store (V_HDA_SNDW_IP_CLOCK_XTAL38P4MHZ, Local0)
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Store (V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL38P4MHZ, Local1)
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Store (V_HDA_SNDW_FRAME_ROW_SIZE_XTAL38P4MHZ, Local2)
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Store (V_HDA_SNDW_FRAME_COL_SIZE_XTAL38P4MHZ, Local3)
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}
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ElseIf (Arg1 == 19200000) {
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Store (V_HDA_SNDW_IP_CLOCK_XTAL19P2MHZ, Local0)
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Store (V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL19P2MHZ, Local1)
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Store (V_HDA_SNDW_FRAME_ROW_SIZE_XTAL19P2MHZ, Local2)
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Store (V_HDA_SNDW_FRAME_COL_SIZE_XTAL19P2MHZ, Local3)
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}
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Else {
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Store (0x00, Local0)
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Store (0x00, Local1)
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Store (0x00, Local2)
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Store (0x00, Local3)
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}
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// Update properties values: "intel-sdw-ip-clock", "mipi-sdw-clock-frequencies-supported",
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// "mipi-sdw-default-frame-row-size", "mipi-sdw-default-frame-col-size"
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// based on detected XTAL (0: 24MHz or 1: 38.4MHz; 2: Unsupported).
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// By default assign values corresponding to XTAL 24MHz.
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// LNK[N] (Arg0) - update property values for selected XTAL (Arg1)
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Store (Local0, SDW_LNK_ENTRY_DATA(Arg0, SDW_INTEL_IP_CLK_INDEX))
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Store (Local1, Index (DeRefOf(SDW_LNK_ENTRY_DATA(Arg0, SDW_MIPI_CLK_FREQ_SUPPORTED_INDEX)), 0))
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Store (Local2, SDW_LNK_ENTRY_DATA(Arg0, SDW_MIPI_DEFAULT_FRAME_ROW_SIZE_INDEX))
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Store (Local3, SDW_LNK_ENTRY_DATA(Arg0, SDW_MIPI_DEFAULT_FRAME_COL_SIZE_INDEX))
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}
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//
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// Update based on PchPolicy
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// Arg0 - Link instance (LNK[N])
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// Arg1 - Data On Active Interval Select (DOAIS)
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// Arg2 - Data On Delay Select (DODS)
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Method(DCFG, 3, NotSerialized) {
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// Update LNK[N] object, "intel-sdw-doais" property value
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// in accordance with SoundWire Link [N] Data On Active Interval Select state in PchPolicy
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Store (Arg1, SDW_LNK_ENTRY_DATA(Arg0, SDW_INTEL_DATA_ON_ACTIVE_INTERVAL_SELECT_INDEX))
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// Update LNK[N] object, "intel-sdw-dods" property value
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// in accordance with SoundWire Link [N] Data On Delay Select state in PchPolicy
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Store (Arg2, SDW_LNK_ENTRY_DATA(Arg0, SDW_INTEL_DATA_ON_DELAY_SELECT))
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}
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//
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// "mipi-sdw-master-count" update
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// Arg0 - SoundWire requester Count value
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Method(SDWU, 1, NotSerialized) {
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Store (Arg0, Index(DeRefOf(Index(DeRefOf(Index(_DSD, 1)), 1)), 1))
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}
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Method (_INI) {
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// Update SoundWire requester Count
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SDWU(\SWMC)
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// Update Link Enable property
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// SWQx - PCH NVS variables set in accordance with PchPolicy (AudioLinkSndwX)
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QCFG(LNK0, \SWQ0, \ACS0)
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QCFG(LNK1, \SWQ1, \ACS1)
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QCFG(LNK2, \SWQ2, \ACS2)
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QCFG(LNK3, \SWQ3, \ACS3)
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// Update XTAL based properties
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// XTAL - PCH NVS variable with XTAL frequency (0 - 24MHz; 1 - 38.4MHz)
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XCFG(LNK0, \XTAL)
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XCFG(LNK1, \XTAL)
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XCFG(LNK2, \XTAL)
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XCFG(LNK3, \XTAL)
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// Update DOAIS and DODS based proparties
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// PCH NVS variables set in accordance with PchPolicy
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DCFG(LNK0, \DAI0, \DOD0)
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DCFG(LNK1, \DAI1, \DOD1)
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DCFG(LNK2, \DAI2, \DOD2)
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DCFG(LNK3, \DAI3, \DOD3)
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}
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Name(_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package (2) {"mipi-sdw-sw-interface-revision", V_HDA_SNDW_SW_INTERFACE_REVISION},
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Package (2) {"mipi-sdw-master-count", 4}
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// Vendor specific parameters (optional)
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},
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// Properties for the SoundWire bus instances
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ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
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Package () {
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Package (2) {"mipi-sdw-link-0-subproperties", "LNK0"},
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Package (2) {"mipi-sdw-link-1-subproperties", "LNK1"},
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Package (2) {"mipi-sdw-link-2-subproperties", "LNK2"},
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Package (2) {"mipi-sdw-link-3-subproperties", "LNK3"}
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}
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})
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Name(LNK0, Package() {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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//
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// Intel specific properties
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//
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Package (2) {"intel-quirk-mask", 0}, // Quirks: [BIT0] - static clock, [BIT1] - bus instance disable (0-No, 1-Yes)
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Package (2) {"intel-sdw-ip-clock", V_HDA_SNDW_IP_CLOCK_XTAL38P4MHZ}, //SoundWire clock value delivered to IP
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Package (2) {"intel-sdw-doais", 1}, //SoundWire Data On Active Interval Select (0 - 3 clock periods, 1 - 4 clock periods, 2 - 5 clock periods, 3 - 6 clock periods)
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Package (2) {"intel-sdw-dods", 1}, //SoundWire Data On Delay Select (0 - 2 clock periods, 1 - 3 clock periods)
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Package (2) {"intel-autonomous-clock-stop", 0}, //SoundWire autonomous clock stop capability (0-Disabled, 1-Enabled)
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//
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// Properties defined as per the MIPI software spec for Link controllers
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//
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Package (2) {"mipi-sdw-clock-stop-mode0-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-stop-mode1-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-frequencies-supported", Package(){V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL38P4MHZ}}, // Package
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Package (2) {"mipi-sdw-default-frame-rate", 48000}, // Integer
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Package (2) {"mipi-sdw-default-frame-row-size", V_HDA_SNDW_FRAME_ROW_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-default-frame-col-size", V_HDA_SNDW_FRAME_COL_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-dynamic-frame-shape", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-command-error-threshold", 16}, // Integer
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}
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})
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Name(LNK1, Package() {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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//
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// Intel specific properties
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//
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Package (2) {"intel-quirk-mask", 0}, // Quirks: [BIT0] - static clock, [BIT1] - bus instance disable (0-No, 1-Yes)
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Package (2) {"intel-sdw-ip-clock", V_HDA_SNDW_IP_CLOCK_XTAL38P4MHZ}, //SoundWire clock value delivered to IP
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Package (2) {"intel-sdw-doais", 1}, //SoundWire Data On Active Interval Select (0 - 3 clock periods, 1 - 4 clock periods, 2 - 5 clock periods, 3 - 6 clock periods)
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Package (2) {"intel-sdw-dods", 1}, //SoundWire Data On Delay Select (0 - 2 clock periods, 1 - 3 clock periods)
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Package (2) {"intel-autonomous-clock-stop", 0}, //SoundWire autonomous clock stop capability (0-Disabled, 1-Enabled)
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//
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// Properties defined as per the MIPI software spec for Link controllers
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//
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Package (2) {"mipi-sdw-clock-stop-mode0-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-stop-mode1-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-frequencies-supported", Package(){V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL38P4MHZ}}, // Package
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Package (2) {"mipi-sdw-default-frame-rate", 48000}, // Integer
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Package (2) {"mipi-sdw-default-frame-row-size", V_HDA_SNDW_FRAME_ROW_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-default-frame-col-size", V_HDA_SNDW_FRAME_COL_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-dynamic-frame-shape", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-command-error-threshold", 16}, // Integer
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}
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})
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Name(LNK2, Package() {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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//
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// Intel specific properties
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//
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Package (2) {"intel-quirk-mask", 0}, // Quirks: [BIT0] - static clock, [BIT1] - bus instance disable (0-No, 1-Yes)
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Package (2) {"intel-sdw-ip-clock", V_HDA_SNDW_IP_CLOCK_XTAL38P4MHZ}, //SoundWire clock value delivered to IP
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Package (2) {"intel-sdw-doais", 1}, //SoundWire Data On Active Interval Select (0 - 3 clock periods, 1 - 4 clock periods, 2 - 5 clock periods, 3 - 6 clock periods)
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Package (2) {"intel-sdw-dods", 1}, //SoundWire Data On Delay Select (0 - 2 clock periods, 1 - 3 clock periods)
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Package (2) {"intel-autonomous-clock-stop", 0}, //SoundWire autonomous clock stop capability (0-Disabled, 1-Enabled)
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//
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// Properties defined as per the MIPI software spec for Link controllers
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//
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Package (2) {"mipi-sdw-clock-stop-mode0-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-stop-mode1-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-frequencies-supported", Package(){V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL38P4MHZ}}, // Package
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Package (2) {"mipi-sdw-default-frame-rate", 48000}, // Integer
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Package (2) {"mipi-sdw-default-frame-row-size", V_HDA_SNDW_FRAME_ROW_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-default-frame-col-size", V_HDA_SNDW_FRAME_COL_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-dynamic-frame-shape", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-command-error-threshold", 16}, // Integer
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}
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})
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Name(LNK3, Package() {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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//
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// Intel specific properties
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//
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Package (2) {"intel-quirk-mask", 0}, // Quirks: [BIT0] - static clock, [BIT1] - bus instance disable (0-No, 1-Yes)
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Package (2) {"intel-sdw-ip-clock", V_HDA_SNDW_IP_CLOCK_XTAL38P4MHZ}, //SoundWire clock value delivered to IP
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Package (2) {"intel-sdw-doais", 1}, //SoundWire Data On Active Interval Select (0 - 3 clock periods, 1 - 4 clock periods, 2 - 5 clock periods, 3 - 6 clock periods)
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Package (2) {"intel-sdw-dods", 1}, //SoundWire Data On Delay Select (0 - 2 clock periods, 1 - 3 clock periods)
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Package (2) {"intel-autonomous-clock-stop", 0}, //SoundWire autonomous clock stop capability (0-Disabled, 1-Enabled)
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//
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// Properties defined as per the MIPI software spec for Link controllers
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//
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Package (2) {"mipi-sdw-clock-stop-mode0-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-stop-mode1-supported", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-clock-frequencies-supported", Package(){V_HDA_SNDW_CLOCK_FREQ_SUPPORTED_XTAL38P4MHZ}}, // Package
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Package (2) {"mipi-sdw-default-frame-rate", 48000}, // Integer
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Package (2) {"mipi-sdw-default-frame-row-size", V_HDA_SNDW_FRAME_ROW_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-default-frame-col-size", V_HDA_SNDW_FRAME_COL_SIZE_XTAL38P4MHZ}, // Integer
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Package (2) {"mipi-sdw-dynamic-frame-shape", 1}, // Integer/Boolean
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Package (2) {"mipi-sdw-command-error-threshold", 16}, // Integer
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}
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})
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}
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}
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