117 lines
4.3 KiB
C
117 lines
4.3 KiB
C
/** @file
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PCH General policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PCH_GENERAL_CONFIG_H_
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#define _PCH_GENERAL_CONFIG_H_
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#define PCH_GENERAL_CONFIG_REVISION 2
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#define PCH_GENERAL_PREMEM_CONFIG_REVISION 3
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extern EFI_GUID gPchGeneralConfigGuid;
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extern EFI_GUID gPchGeneralPreMemConfigGuid;
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#pragma pack (push,1)
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enum PCH_RESERVED_PAGE_ROUTE {
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PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
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PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
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};
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/**
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PCH General Configuration
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<b>Revision 1</b>: - Initial version.
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<b>Revision 2</b>: - Added AcpiL6dPmeHandling
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This member describes whether or not the Compatibility Revision ID (CRID) feature
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of PCH should be enabled. <b>0: Disable</b>; 1: Enable
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**/
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UINT32 Crid : 1;
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/**
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Set to enable low latency of legacy IO.
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Some systems require lower IO latency irrespective of power.
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This is a tradeoff between power and IO latency.
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@note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
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and ITSS Clock Gating are forced to disabled.
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<b>0: Disable</b>, 1: Enable
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**/
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UINT32 LegacyIoLowLatency : 1;
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/**
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Enables _L6D ACPI handler.
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PME GPE is shared by multiple devices So BIOS must verify the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit
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<b>0: Disable</b>, 1: Enable
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**/
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UINT32 AcpiL6dPmeHandling : 1;
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UINT32 RsvdBits0 : 29; ///< Reserved bits
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} PCH_GENERAL_CONFIG;
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/**
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PCH General Pre-Memory Configuration
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<b>Revision 1</b>: - Initial version.
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<b>Revision 2</b>: - Added GpioOverride.
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<b>Revision 3</b>: - Added IoeDebugEn, PmodeClkEn
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
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**/
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UINT32 Port80Route : 1;
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UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SSC for A0 PO
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/**
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Gpio override Level
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-- <b>0: Disable</b>;
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- 1: Override Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase
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- 2: Override Level 2 - Reserved for future use
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**/
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UINT32 GpioOverride : 3;
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/**
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Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link and clock will keep up for debug
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<b>0: Disable</b>; 1: Enable
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**/
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UINT32 IoeDebugEn : 1;
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/**
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Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use
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<b>0: Disable</b>; 1: Enable
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**/
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UINT32 PmodeClkEn : 1;
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UINT32 RsvdBits0 : 25; ///< Reserved bits
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} PCH_GENERAL_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _PCH_GENERAL_CONFIG_H_
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