376 lines
27 KiB
C
376 lines
27 KiB
C
/** @file
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Print whole PCH_POLICY_PPI
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2014 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "PeiPchPolicyLibrary.h"
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#include <Library/GpioPrivateLib.h>
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#include <Library/ChipsetInitLib.h>
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/**
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Print PCH_HSIO_CONFIG.
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@param[in] HsioConfig Pointer to a PCH_HSIO_CONFIG that provides the eSPI setting
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**/
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VOID
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PchPrintHsioConfig (
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IN CONST PCH_HSIO_CONFIG *HsioConfig
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)
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{
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PCH_HSIO_VER_INFO *BiosChipsetInitVerInfoPtr;
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DEBUG ((DEBUG_INFO, "------------------ PCH HSIO Config ------------------\n"));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Pointer = %x\n", HsioConfig->ChipsetInitBinPtr));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Length = %x\n", HsioConfig->ChipsetInitBinLen));
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BiosChipsetInitVerInfoPtr = (PCH_HSIO_VER_INFO *) HsioConfig->ChipsetInitBinPtr;
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if (HsioConfig->ChipsetInitBinPtr && HsioConfig->ChipsetInitBinLen) {
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base CRC = %x\n", BiosChipsetInitVerInfoPtr->BaseCrc));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM CRC = %x\n", BiosChipsetInitVerInfoPtr->OemCrc));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary SUS CRC = %x\n", BiosChipsetInitVerInfoPtr->SusCrc));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Version = %x\n", BiosChipsetInitVerInfoPtr->Version));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Product = %x\n", BiosChipsetInitVerInfoPtr->Product));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Metal Layer = %x\n", BiosChipsetInitVerInfoPtr->MetalLayer));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base Layer = %x\n", BiosChipsetInitVerInfoPtr->BaseLayer));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM Version = %x\n", BiosChipsetInitVerInfoPtr->OemVersion));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Debug Mode = %x\n", BiosChipsetInitVerInfoPtr->DebugMode));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM CRC Valid = %x\n", BiosChipsetInitVerInfoPtr->OemCrcValid));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary SUS CRC Valid = %x\n", BiosChipsetInitVerInfoPtr->SusCrcValid));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base CRC Valid = %x\n", BiosChipsetInitVerInfoPtr->BaseCrcValid));
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DEBUG ((DEBUG_INFO, " ChipsetInit Binary Use CSME ChipsetInit = %x\n", BiosChipsetInitVerInfoPtr->Reserved & BIT0));
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}
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}
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/**
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Print PCH_PCIE_CONFIG and serial out.
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@param[in] PchPcieConfig Pointer to a PCH_PCIE_CONFIG that provides the platform settings
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**/
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VOID
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PchPrintPcieConfig (
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IN CONST PCH_PCIE_CONFIG *PchPcieConfig
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)
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{
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UINT32 Index;
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UINT32 RpIndex;
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DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config ------------------\n"));
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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DEBUG ((DEBUG_INFO, " RootPort[%d] HotPlug= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.HotPlug));
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DEBUG ((DEBUG_INFO, " RootPort[%d] PmSci= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PmSci));
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DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqDetect= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.ClkReqDetect));
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DEBUG ((DEBUG_INFO, " RootPort[%d] MrlSensorPresent = %d\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.MrlSensorPresent));
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DEBUG ((DEBUG_INFO, " RootPort[%d] UnsupportedRequestReport= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.UnsupportedRequestReport));
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DEBUG ((DEBUG_INFO, " RootPort[%d] FatalErrorReport= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.FatalErrorReport));
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DEBUG ((DEBUG_INFO, " RootPort[%d] NoFatalErrorReport= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.NoFatalErrorReport));
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DEBUG ((DEBUG_INFO, " RootPort[%d] CorrectableErrorReport= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.CorrectableErrorReport));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnFatalError= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.SystemErrorOnFatalError));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnNonFatalError= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.SystemErrorOnNonFatalError));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnCorrectableError= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.SystemErrorOnCorrectableError));
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DEBUG ((DEBUG_INFO, " RootPort[%d] MaxPayload= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.MaxPayload));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SlotImplemented= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.SlotImplemented));
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DEBUG ((DEBUG_INFO, " RootPort[%d] AcsEnabled= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.AcsEnabled));
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DEBUG ((DEBUG_INFO, " RootPort[%d] PtmEnabled= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PtmEnabled));
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DEBUG ((DEBUG_INFO, " RootPort[%d] AdvancedErrorReporting= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.AdvancedErrorReporting));
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DEBUG ((DEBUG_INFO, " RootPort[%d] TransmitterHalfSwing= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.TransmitterHalfSwing));
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DEBUG ((DEBUG_INFO, " RootPort[%d] PcieSpeed= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieSpeed));
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DEBUG ((DEBUG_INFO, " RootPort[%d] PhysicalSlotNumber= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PhysicalSlotNumber));
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DEBUG ((DEBUG_INFO, " RootPort[%d] CompletionTimeout= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.CompletionTimeout));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Aspm= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.Aspm));
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DEBUG ((DEBUG_INFO, " RootPort[%d] L1Substates= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.L1Substates));
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DEBUG ((DEBUG_INFO, " RootPort[%d] LtrEnable= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.LtrEnable));
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DEBUG ((DEBUG_INFO, " RootPort[%d] LtrConfigLock= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrConfigLock));
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DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxSnoopLatency= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxSnoopLatency));
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DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxNoSnoopLatency= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxNoSnoopLatency));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMode= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideMode));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMultiplier= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideMultiplier));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideValue= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.SnoopLatencyOverrideValue));
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DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMode= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideMode));
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DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMultiplier= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideMultiplier));
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DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideValue= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.NonSnoopLatencyOverrideValue));
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DEBUG ((DEBUG_INFO, " RootPort[%d] ForceLtrOverride= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.ForceLtrOverride));
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DEBUG ((DEBUG_INFO, " RootPort[%d] DetectTimeoutMs= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.DetectTimeoutMs));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitScale= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.SlotPowerLimitScale));
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DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitValue= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.SlotPowerLimitValue));
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DEBUG ((DEBUG_INFO, " RootPort[%d] EnableCpm= %x\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.EnableCpm));
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DEBUG ((DEBUG_INFO, " RootPort[%d] FormFactor = %d\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.FormFactor));
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DEBUG ((DEBUG_INFO, " RootPort[%d] EnablePeerMemoryWrite = %d\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.EnablePeerMemoryWrite));
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DEBUG ((DEBUG_INFO, " RootPort[%d] ClockGating = %d\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.ClockGating));
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DEBUG ((DEBUG_INFO, " RootPort[%d] PowerGating = %d\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PowerGating));
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DEBUG ((DEBUG_INFO, " RootPort[%d] LinkDownGpios = %d\n", Index, PchPcieConfig->RootPort[Index].PcieRpCommonConfig.LinkDownGpios));
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}
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for (RpIndex = 0; RpIndex < GetPchMaxPciePortNum(); RpIndex++) {
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DEBUG ((DEBUG_INFO, " RootPort[%d] OverrideEqualizationDefaults: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.OverrideEqualizationDefaults));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 PcieLinkEqMethod: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.PcieLinkEqMethod));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 PcieLinkEqMethod: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.PcieLinkEqMethod));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 PcieLinkEqMethod: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.PcieLinkEqMethod));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 PcieLinkEqMode: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.PcieLinkEqMode));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 PcieLinkEqMode: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.PcieLinkEqMode));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 PcieLinkEqMode: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.PcieLinkEqMode));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 Ph1DownstreamPortTransmitterPreset: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.Ph1DownstreamPortTransmitterPreset));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 Ph1DownstreamPortTransmitterPreset: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.Ph1DownstreamPortTransmitterPreset));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 Ph1DownstreamPortTransmitterPreset: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.Ph1DownstreamPortTransmitterPreset));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 Ph1UpstreamPortTransmitterPreset: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.Ph1UpstreamPortTransmitterPreset));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 Ph1UpstreamPortTransmitterPreset: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.Ph1UpstreamPortTransmitterPreset));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 Ph1UpstreamPortTransmitterPreset: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.Ph1UpstreamPortTransmitterPreset));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 Ph3NumberOfPresetsOrCoefficients: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.Ph3NumberOfPresetsOrCoefficients));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 Ph3NumberOfPresetsOrCoefficients: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.Ph3NumberOfPresetsOrCoefficients));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 Ph3NumberOfPresetsOrCoefficients: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.Ph3NumberOfPresetsOrCoefficients));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 EqPh3Bypass: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.EqPh3Bypass));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 EqPh3Bypass: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.EqPh3Bypass));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 EqPh3Bypass: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.EqPh3Bypass));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 EqPh23Bypass: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.EqPh23Bypass));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 EqPh23Bypass: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.EqPh23Bypass));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 EqPh23Bypass: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.EqPh23Bypass));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 PcetTimer: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.PCETTimer));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 PcetTimer: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.PCETTimer));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 PcetTimer: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.PCETTimer));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3 TsLockTimer: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.TsLockTimer));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen4 TsLockTimer: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.TsLockTimer));
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DEBUG ((DEBUG_INFO, " RootPort[%d] Gen5 TsLockTimer: %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.TsLockTimer));
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for (Index = 0; Index < PCIE_LINK_EQ_COEFFICIENTS_MAX; Index++) {
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DEBUG ((DEBUG_INFO,
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"RootPort[%d] Gen3 Phase 3 Coefficient %d, pre-cursor = %d, post-cursor = %d\n",
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RpIndex,
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Index,
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PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.Ph3CoefficientsList[Index].PreCursor,
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PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.Ph3CoefficientsList[Index].PostCursor));
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DEBUG ((DEBUG_INFO,
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"RootPort[%d] Gen4 Phase 3 Coefficient %d, pre-cursor = %d, post-cursor = %d\n",
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RpIndex,
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Index,
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PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.Ph3CoefficientsList[Index].PreCursor,
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PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.Ph3CoefficientsList[Index].PostCursor));
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DEBUG ((DEBUG_INFO,
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"RootPort[%d] Gen5 Phase 3 Coefficient %d, pre-cursor = %d, post-cursor = %d\n",
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RpIndex,
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Index,
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PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.Ph3CoefficientsList[Index].PreCursor,
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PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.Ph3CoefficientsList[Index].PostCursor));
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}
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for (Index = 0; Index < PCIE_LINK_EQ_PRESETS_MAX; Index++) {
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen3 Phase 3 Preset %d = %d\n", RpIndex, Index, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.Ph3PresetList[Index]));
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen4 Phase 3 Preset %d = %d\n", RpIndex, Index, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.Ph3PresetList[Index]));
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen5 Phase 3 Preset %d = %d\n", RpIndex, Index, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.Ph3PresetList[Index]));
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}
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen3 LocalTransmitterOverrideEnable = %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.LocalTransmitterOverrideEnable));
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen4 LocalTransmitterOverrideEnable = %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.LocalTransmitterOverrideEnable));
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen5 LocalTransmitterOverrideEnable = %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.LocalTransmitterOverrideEnable));
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen3 Ph2LocalTransmitterOverridePreset = %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen3LinkEqPlatformSettings.Ph2LocalTransmitterOverridePreset));
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen4 Ph2LocalTransmitterOverridePreset = %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen4LinkEqPlatformSettings.Ph2LocalTransmitterOverridePreset));
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DEBUG ((DEBUG_INFO, "RootPort[%d] Gen5 Ph2LocalTransmitterOverridePreset = %d\n", RpIndex, PchPcieConfig->RootPort[RpIndex].PcieRpCommonConfig.PcieGen5LinkEqPlatformSettings.Ph2LocalTransmitterOverridePreset));
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}
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DEBUG ((DEBUG_INFO, " EnablePort8xhDecode= %x\n", PchPcieConfig->PcieCommonConfig.EnablePort8xhDecode));
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DEBUG ((DEBUG_INFO, " PchPciePort8xhDecodePortIndex= %x\n", PchPcieConfig->PchPciePort8xhDecodePortIndex));
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DEBUG ((DEBUG_INFO, " ComplianceTestMode= %x\n", PchPcieConfig->PcieCommonConfig.ComplianceTestMode));
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DEBUG ((DEBUG_INFO, " RpFunctionSwap= %x\n", PchPcieConfig->PcieCommonConfig.RpFunctionSwap));
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}
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/**
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Print RST_CONFIG and serial out.
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@param[in] RstConfig Pointer to a RST_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintRstConfig (
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IN CONST RST_CONFIG *RstConfig
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)
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{
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UINT32 Index;
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DEBUG ((DEBUG_INFO, "--------------------- RST Config ------------------------\n"));
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DEBUG ((DEBUG_INFO, " Raid0= %x\n", RstConfig->Raid0));
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DEBUG ((DEBUG_INFO, " Raid1= %x\n", RstConfig->Raid1));
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DEBUG ((DEBUG_INFO, " Raid10= %x\n", RstConfig->Raid10));
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DEBUG ((DEBUG_INFO, " Raid5= %x\n", RstConfig->Raid5));
|
|
DEBUG ((DEBUG_INFO, " Irrt= %x\n", RstConfig->Irrt));
|
|
DEBUG ((DEBUG_INFO, " OromUiBanner= %x\n", RstConfig->OromUiBanner));
|
|
DEBUG ((DEBUG_INFO, " OromUiDelay= %x\n", RstConfig->OromUiDelay));
|
|
DEBUG ((DEBUG_INFO, " HddUnlock= %x\n", RstConfig->HddUnlock));
|
|
DEBUG ((DEBUG_INFO, " LedLocate= %x\n", RstConfig->LedLocate));
|
|
DEBUG ((DEBUG_INFO, " IrrtOnly= %x\n", RstConfig->IrrtOnly));
|
|
DEBUG ((DEBUG_INFO, " SmartStorage= %x\n", RstConfig->SmartStorage));
|
|
DEBUG ((DEBUG_INFO, " LegacyOrom= %x\n", RstConfig->LegacyOrom));
|
|
DEBUG ((DEBUG_INFO, " OptaneMemory= %x\n", RstConfig->OptaneMemory));
|
|
DEBUG ((DEBUG_INFO, " CpuAttachedStorage= %x\n", RstConfig->CpuAttachedStorage));
|
|
|
|
for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
|
|
DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].Enable = %x\n", Index, RstConfig->HardwareRemappedStorageConfig[Index].Enable));
|
|
DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].RstPcieStoragePort = %x\n", Index, RstConfig->HardwareRemappedStorageConfig[Index].RstPcieStoragePort));
|
|
DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].DeviceResetDelay = %x\n", Index, RstConfig->HardwareRemappedStorageConfig[Index].DeviceResetDelay));
|
|
}
|
|
}
|
|
|
|
/**
|
|
Print PCH_LOCK_DOWN_CONFIG and serial out.
|
|
|
|
@param[in] LockDownConfig Pointer to a PCH_LOCK_DOWN_CONFIG that provides the platform setting
|
|
**/
|
|
VOID
|
|
PchPrintLockDownConfig (
|
|
IN CONST PCH_LOCK_DOWN_CONFIG *LockDownConfig
|
|
)
|
|
{
|
|
DEBUG ((DEBUG_INFO, "------------------ PCH Lock Down Config ------------------\n"));
|
|
DEBUG ((DEBUG_INFO, " GlobalSmi= %x\n", LockDownConfig->GlobalSmi));
|
|
DEBUG ((DEBUG_INFO, " BiosInterface= %x\n", LockDownConfig->BiosInterface));
|
|
DEBUG ((DEBUG_INFO, " BiosLock= %x\n", LockDownConfig->BiosLock));
|
|
DEBUG ((DEBUG_INFO, " SpiEiss= %x\n", LockDownConfig->SpiEiss));
|
|
DEBUG ((DEBUG_INFO, " UnlockGpioPads= %x\n", LockDownConfig->UnlockGpioPads));
|
|
}
|
|
|
|
/**
|
|
Print PCH_GENERAL_CONFIG and serial out.
|
|
|
|
@param[in] PchGeneralConfig Pointer to a PCH_GENERAL_CONFIG that provides the platform setting
|
|
**/
|
|
VOID
|
|
PchPrintGeneralConfig (
|
|
IN CONST PCH_GENERAL_CONFIG *PchGeneralConfig
|
|
)
|
|
{
|
|
DEBUG ((DEBUG_INFO, "------------------ PCH General Config ------------------\n"));
|
|
DEBUG ((DEBUG_INFO, " Crid= %x\n", PchGeneralConfig->Crid));
|
|
DEBUG ((DEBUG_INFO, " LegacyIoLowLatency = %x\n", PchGeneralConfig->LegacyIoLowLatency));
|
|
DEBUG ((DEBUG_INFO, " AcpiL6dPmeHandling = %x\n", PchGeneralConfig->AcpiL6dPmeHandling));
|
|
}
|
|
|
|
/**
|
|
Print PCH_FLASH_PROTECTION_CONFIG and serial out.
|
|
|
|
@param[in] FlashProtectConfig Pointer to a PCH_FLASH_PROTECTION_CONFIG that provides the platform setting
|
|
**/
|
|
VOID
|
|
PchPrintFlashProtectionConfig (
|
|
IN CONST PCH_FLASH_PROTECTION_CONFIG *FlashProtectConfig
|
|
)
|
|
{
|
|
UINT32 Index;
|
|
|
|
DEBUG ((DEBUG_INFO, "------------------ PCH Flash Protection Config ------------------\n"));
|
|
for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; ++Index) {
|
|
DEBUG ((DEBUG_INFO, " WriteProtectionEnable[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].WriteProtectionEnable));
|
|
DEBUG ((DEBUG_INFO, " ReadProtectionEnable[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ReadProtectionEnable));
|
|
DEBUG ((DEBUG_INFO, " ProtectedRangeLimit[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ProtectedRangeLimit));
|
|
DEBUG ((DEBUG_INFO, " ProtectedRangeBase[%d] = %x\n", Index, FlashProtectConfig->ProtectRange[Index].ProtectedRangeBase));
|
|
}
|
|
}
|
|
|
|
/**
|
|
Print PCH_FIVR_CONFIG.
|
|
|
|
@param[in] FivrConfig Pointer to a PCH_FIVR_CONFIG that provides the FIVR settings
|
|
|
|
**/
|
|
VOID
|
|
PchPrintFivrConfig (
|
|
IN CONST PCH_FIVR_CONFIG *FivrConfig
|
|
)
|
|
{
|
|
DEBUG ((DEBUG_INFO, "------------------ PCH FIVR Config ------------------\n"));
|
|
DEBUG ((DEBUG_INFO, " ExtV1p05Rail:\n"));
|
|
DEBUG ((DEBUG_INFO, " EnabledStates = %x\n", FivrConfig->ExtV1p05Rail.EnabledStates));
|
|
DEBUG ((DEBUG_INFO, " SupportedVoltageStates = %x\n", FivrConfig->ExtV1p05Rail.SupportedVoltageStates));
|
|
DEBUG ((DEBUG_INFO, " Voltage = %x\n", FivrConfig->ExtV1p05Rail.Voltage));
|
|
DEBUG ((DEBUG_INFO, " IccMax = %x\n", FivrConfig->ExtV1p05Rail.IccMax));
|
|
DEBUG ((DEBUG_INFO, " ExtVnnRail:\n"));
|
|
DEBUG ((DEBUG_INFO, " EnabledStates = %x\n", FivrConfig->ExtVnnRail.EnabledStates));
|
|
DEBUG ((DEBUG_INFO, " SupportedVoltageStates = %x\n", FivrConfig->ExtVnnRail.SupportedVoltageStates));
|
|
DEBUG ((DEBUG_INFO, " Voltage = %x\n", FivrConfig->ExtVnnRail.Voltage));
|
|
DEBUG ((DEBUG_INFO, " IccMax = %x\n", FivrConfig->ExtVnnRail.IccMax));
|
|
DEBUG ((DEBUG_INFO, " ExtVnnRailSx:\n"));
|
|
DEBUG ((DEBUG_INFO, " EnabledStates = %x\n", FivrConfig->ExtVnnRailSx.EnabledStates));
|
|
DEBUG ((DEBUG_INFO, " Voltage = %x\n", FivrConfig->ExtVnnRailSx.Voltage));
|
|
DEBUG ((DEBUG_INFO, " IccMax = %x\n", FivrConfig->ExtVnnRailSx.IccMax));
|
|
DEBUG ((DEBUG_INFO, " VccinAux:\n"));
|
|
DEBUG ((DEBUG_INFO, " LowToHighCurModeVolTranTime = %x\n", FivrConfig->VccinAux.LowToHighCurModeVolTranTime));
|
|
DEBUG ((DEBUG_INFO, " RetToHighCurModeVolTranTime = %x\n", FivrConfig->VccinAux.RetToHighCurModeVolTranTime));
|
|
DEBUG ((DEBUG_INFO, " RetToLowCurModeVolTranTime = %x\n", FivrConfig->VccinAux.RetToLowCurModeVolTranTime));
|
|
DEBUG ((DEBUG_INFO, " OffToHighCurModeVolTranTime = %x\n", FivrConfig->VccinAux.OffToHighCurModeVolTranTime));
|
|
DEBUG ((DEBUG_INFO, " FivrDynPm = %x\n", FivrConfig->FivrDynPm));
|
|
DEBUG ((DEBUG_INFO, " BypassFivrConfig = %x\n", FivrConfig->BypassFivrConfig));
|
|
}
|
|
|
|
/**
|
|
Print whole PCH config blocks and serial out.
|
|
|
|
@param[in] SiPolicyPpi The RC Policy PPI instance
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
PchPrintPolicyPpi (
|
|
IN SI_POLICY_PPI *SiPolicyPpi
|
|
)
|
|
{
|
|
DEBUG_CODE_BEGIN();
|
|
UINT32 SataCtrlIndex;
|
|
EFI_STATUS Status;
|
|
PCH_GENERAL_CONFIG *PchGeneralConfig;
|
|
PCH_PCIE_CONFIG *PchPcieConfig;
|
|
RST_CONFIG *RstConfig;
|
|
PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
|
|
PCH_LOCK_DOWN_CONFIG *LockDownConfig;
|
|
PCH_HSIO_CONFIG *HsioConfig;
|
|
PCH_FIVR_CONFIG *FivrConfig;
|
|
|
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
|
|
ASSERT_EFI_ERROR (Status);
|
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPchPcieConfigGuid, (VOID *) &PchPcieConfig);
|
|
ASSERT_EFI_ERROR (Status);
|
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
|
|
ASSERT_EFI_ERROR (Status);
|
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
|
|
ASSERT_EFI_ERROR (Status);
|
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gFivrConfigGuid, (VOID *) &FivrConfig);
|
|
ASSERT_EFI_ERROR (Status);
|
|
Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gHsioConfigGuid, (VOID *) &HsioConfig);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
DEBUG ((DEBUG_INFO, "------------------------ PCH Print Policy Start ------------------------\n"));
|
|
DEBUG ((DEBUG_INFO, " Revision= %x\n", SiPolicyPpi->TableHeader.Header.Revision));
|
|
|
|
PchPrintGeneralConfig (PchGeneralConfig);
|
|
PchPrintPcieConfig (PchPcieConfig);
|
|
|
|
for (SataCtrlIndex = 0; SataCtrlIndex < MaxSataControllerNum(); SataCtrlIndex++) {
|
|
RstConfig = GetPchRstConfig(SiPolicyPpi, SataCtrlIndex);
|
|
PchPrintRstConfig (RstConfig);
|
|
}
|
|
PchPrintLockDownConfig (LockDownConfig);
|
|
PchPrintFlashProtectionConfig (FlashProtectionConfig);
|
|
PchPrintHsioConfig (HsioConfig);
|
|
PchPrintFivrConfig (FivrConfig);
|
|
|
|
DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protocol End --------------------------\n"));
|
|
DEBUG_CODE_END();
|
|
}
|