252 lines
8.3 KiB
C
252 lines
8.3 KiB
C
/** @file
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SEC PCH library in C.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchPciBdfLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/SerialIoUartLib.h>
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#include <Library/PmcLib.h>
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#include <Library/PrintLib.h>
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#include <Library/PsfSocLib.h>
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#include <Library/PmcPrivateLib.h>
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#include <Library/PeiSerialIoInitLib.h>
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#include <Library/SerialIoAccessLib.h>
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#include <PchReservedResources.h>
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#include <Register/PchRegs.h>
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#include <Register/PchPcrRegs.h>
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#include <Register/P2sbRegs.h>
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#include <Register/SmbusRegs.h>
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#include <Register/RtcRegs.h>
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#include <IndustryStandard/Pci30.h>
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#include <SerialIoDevices.h>
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#if FixedPcdGetBool(PcdFspBinaryEnable) == 1
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/**
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Serial Io Uart Debug Configuration Wrapper
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@param[out] UartDeviceConfig A pointer to the SERIAL_IO_UART_CONFIG.
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@param[out] SerialIoUartDebugEnable Serial Io Uart Debug Enable/Disable.
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@param[out] SerialIoUartNumber The Number of Serial Io Uart.
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@param[out] SerialIoUartPciMmioBase MMIO Base Address by default in PCI Mode.
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**/
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VOID
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SerialIoUartDebugConfigurationWrapper (
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OUT SERIAL_IO_UART_CONFIG *UartDeviceConfig,
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OUT UINT8 *SerialIoUartDebugEnable,
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OUT UINT8 *SerialIoUartNumber,
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OUT UINT32 *SerialIoUartPciMmioBase
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);
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/**
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Serial Io Additional Uart Configuration Wrapper
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Allows to configure another UART in FSPT
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@param[out] UartEnable Serial Io Additional Uart Enable/Disable.
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@param[out] UartDeviceConfig A pointer to the SERIAL_IO_UART_CONFIG.
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@param[out] SerialIoUartNumber The Number of Serial Io Uart.
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@param[out] SerialIoUartPciMmioBase MMIO Base Address by default in PCI Mode
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**/
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VOID
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SerialIo2ndUartConfigurationWrapper (
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OUT UINT8 *UartEnable,
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OUT SERIAL_IO_UART_CONFIG *UartDeviceConfig,
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OUT UINT8 *SerialIoUartNumber,
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OUT UINT32 *SerialIoUartPciMmioBase
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);
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/**
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Serial Io Spi Configuration Wrapper
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@param[out] SpiDeviceConfig A pointer to the SERIAL_IO_SPI_CONFIG.
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@param[out] SerialIoSpiNumber The Number of Serial Io Spi.
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@param[out] SerialIoSpiMmioBase MMIO Base Address by default in PCI Mode
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**/
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VOID
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SerialIoSpiConfigurationWrapper (
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OUT SERIAL_IO_SPI_CONFIG *SpiDeviceConfig,
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OUT UINT8 *SerialIoSpiNumber,
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OUT UINT32 *SerialIoSpiMmioBase
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);
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#else
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#include <Library/SerialIoUartDebugPropertyPcdLib.h>
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#endif
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/**
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This is helper function to initialize SerialIoSpi in early init.
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**/
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VOID
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EFIAPI
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SerialIoSpiEarlyinitalization (
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VOID
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)
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{
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#if FixedPcdGetBool(PcdFspBinaryEnable) == 1
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SERIAL_IO_SPI_CONFIG SpiDeviceConfig;
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UINT8 SerialIoSpiNumber;
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UINT32 SerialIoSpiMmioBase;
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UINT64 SerialIoSpiPciCfgBase;
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SerialIoSpiConfigurationWrapper (&SpiDeviceConfig, &SerialIoSpiNumber, &SerialIoSpiMmioBase);
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if (SpiDeviceConfig.Mode == 0) {
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return;
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}
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SerialIoSpiPciCfgBase = GetSerialIoSpiPciCfg (SerialIoSpiNumber);
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PciSegmentWrite32 (SerialIoSpiPciCfgBase + PCI_BASE_ADDRESSREG_OFFSET, SerialIoSpiMmioBase);
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PciSegmentWrite32 (SerialIoSpiPciCfgBase + PCI_BASE_ADDRESSREG_OFFSET + 4, 0x0);
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SerialIoSpiConfiguration (SerialIoSpiNumber, &SpiDeviceConfig, TRUE);
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#endif
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}
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/**
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This is helper function to initialize SerialIoUart in early init.
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**/
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VOID
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EFIAPI
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SerialIoUartDebugConfiguration (
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VOID
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)
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{
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SERIAL_IO_UART_CONFIG UartDeviceConfig;
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UINT8 SerialIoUartDebugEnable;
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UINT8 SerialIoUartNumber;
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UINT32 SerialIoUartPciMmioBase;
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CHAR8 CarInitBuffer[32];
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#if FixedPcdGetBool(PcdFspBinaryEnable) == 1
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UINT8 AdditionalUartEnabled;
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AsciiSPrint (CarInitBuffer, sizeof (CarInitBuffer), "FSP-T: CAR Init\n");
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SerialIoUartDebugConfigurationWrapper (&UartDeviceConfig, &SerialIoUartDebugEnable, &SerialIoUartNumber, &SerialIoUartPciMmioBase);
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#else
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AsciiSPrint (CarInitBuffer, sizeof (CarInitBuffer), "CAR Init\n");
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SerialIoUartDebugEnable = SerialIoUartDebugPcdGetDebugEnable ();
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SerialIoUartPciMmioBase = SerialIoUartDebugPcdGetPciDefaultMmioBase ();
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SerialIoUartDebugPcdGetDeviceConfig (&UartDeviceConfig, &SerialIoUartNumber);
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#endif
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UartDeviceConfig.DBG2 = FALSE;
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UartDeviceConfig.DmaEnable = FALSE;
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//
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// Initialize SerialIo UART for debug message
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//
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if (SerialIoUartDebugEnable == 1) {
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if (UartDeviceConfig.Mode == SerialIoUartPci) {
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SerialIoUartSetMmioInPciMode (SerialIoUartNumber, (UINT64)SerialIoUartPciMmioBase);
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}
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SerialIoUartConfiguration (SerialIoUartNumber, &UartDeviceConfig, TRUE);
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SerialIoUartWrite (SerialIoUartNumber, (UINT8 *)CarInitBuffer, AsciiStrLen (CarInitBuffer));
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}
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#if FixedPcdGetBool(PcdFspBinaryEnable) == 1
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SerialIo2ndUartConfigurationWrapper (&AdditionalUartEnabled, &UartDeviceConfig, &SerialIoUartNumber, &SerialIoUartPciMmioBase);
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if (AdditionalUartEnabled == 1) {
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if (UartDeviceConfig.Mode == SerialIoUartPci) {
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SerialIoUartSetMmioInPciMode (SerialIoUartNumber, (UINT64)SerialIoUartPciMmioBase);
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}
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SerialIoUartConfiguration (SerialIoUartNumber, &UartDeviceConfig, TRUE);
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}
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#endif
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}
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/**
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This function do the PCH cycle decoding initialization.
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**/
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VOID
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EFIAPI
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EarlyCycleDecoding (
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VOID
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)
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{
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UINT64 P2sbBase;
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UINT64 SmbusBase;
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//
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// Enable PCR base address in PCH
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//
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P2sbBase = P2sbPciCfgBase ();
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PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBREG_BAR, PCH_PCR_BASE_ADDRESS);
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//
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// Enable P2SB MSE
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//
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PciSegmentOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// Program PWRM BASE
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//
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PmcSetPwrmBase (PmcPciCfgBase (), PCH_PWRM_BASE_ADDRESS);
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//
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// Program ACPI Base.
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//
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PsfSetPmcAbase (PsfPmcPort (), PcdGet16 (PcdAcpiBaseAddress));
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//
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// Program and Enable TCO Base
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//
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PchTcoBaseSet (PcdGet16 (PcdTcoBaseAddress));
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SmbusBase = SmbusPciCfgBase ();
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//
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// Set SMBus PCI 0x64 = 0x0A0A0000
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//
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PciSegmentWrite32 (SmbusBase + R_SMBUS_CFG_64, 0x0A0A0000);
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//
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// Initialize SMBUS IO BAR
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//
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PciSegmentWrite16 (SmbusBase + R_SMBUS_CFG_BASE, PcdGet16 (PcdSmbusBaseAddress));
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//
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// Enable the Smbus I/O Enable
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//
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PciSegmentOr8 (SmbusBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE);
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//
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// Enable the SMBUS Controller
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//
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PciSegmentOr8 (SmbusBase + R_SMBUS_CFG_HOSTC, B_SMBUS_CFG_HOSTC_HST_EN);
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//
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// Enable the upper 128-byte bank of RTC RAM.
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// PCR [RTC] + 0x3400 [2] = 1
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//
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PchPcrAndThenOr32 (PID_RTC_HOST, R_RTC_PCR_CONF, (UINT32) ~0, B_RTC_PCR_CONF_UCMOS_EN);
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}
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