97 lines
3.2 KiB
C
97 lines
3.2 KiB
C
/** @file
|
|
eSPI SMI Dispatch header
|
|
|
|
@copyright
|
|
INTEL CONFIDENTIAL
|
|
Copyright 2019-2021 Intel Corporation.
|
|
|
|
The source code contained or described herein and all documents related to the
|
|
source code ("Material") are owned by Intel Corporation or its suppliers or
|
|
licensors. Title to the Material remains with Intel Corporation or its suppliers
|
|
and licensors. The Material may contain trade secrets and proprietary and
|
|
confidential information of Intel Corporation and its suppliers and licensors,
|
|
and is protected by worldwide copyright and trade secret laws and treaty
|
|
provisions. No part of the Material may be used, copied, reproduced, modified,
|
|
published, uploaded, posted, transmitted, distributed, or disclosed in any way
|
|
without Intel's prior express written permission.
|
|
|
|
No license under any patent, copyright, trade secret or other intellectual
|
|
property right is granted to or conferred upon you by disclosure or delivery
|
|
of the Materials, either expressly, by implication, inducement, estoppel or
|
|
otherwise. Any license under such intellectual property rights must be
|
|
express and approved by Intel in writing.
|
|
|
|
Unless otherwise agreed by Intel in writing, you may not remove or alter
|
|
this notice or any other notice embedded in Materials by Intel or
|
|
Intel's suppliers or licensors in any way.
|
|
|
|
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
|
|
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
|
|
the terms of your license agreement with Intel or your vendor. This file may
|
|
be modified by the user, subject to additional terms of the license agreement.
|
|
|
|
@par Specification
|
|
**/
|
|
|
|
#ifndef _PCH_SMI_HELPER_H_
|
|
#define _PCH_SMI_HELPER_H_
|
|
#include <Uefi/UefiBaseType.h>
|
|
|
|
/**
|
|
Get Root Port physical Number by CPU or PCH Pcie Root Port Device and Function Number
|
|
|
|
@param[in] RpDev Root port device number.
|
|
@param[in] RpFun Root port function number.
|
|
@param[out] RpNumber Return corresponding physical Root Port index (0-based)
|
|
**/
|
|
VOID
|
|
GetPcieRpNumber (
|
|
IN UINTN RpDev,
|
|
IN UINTN RpFun,
|
|
OUT UINTN *RpNumber
|
|
);
|
|
|
|
/**
|
|
Get CPU or PCH Pcie Root Port Device and Function Number by Root Port physical Number
|
|
|
|
@param[in] RpNumber Root port physical number. (0-based)
|
|
@param[out] RpDev Return corresponding root port device number.
|
|
@param[out] RpFun Return corresponding root port function number.
|
|
**/
|
|
VOID
|
|
GetPcieRpDevFun (
|
|
IN UINTN RpIndex,
|
|
OUT UINTN *RpDev,
|
|
OUT UINTN *RpFun
|
|
);
|
|
|
|
/**
|
|
For each CPU PCIE RP clear PME SCI status
|
|
**/
|
|
VOID
|
|
ClearPcieSciForCpuRp (
|
|
VOID
|
|
);
|
|
|
|
/**
|
|
For each PCIE RP clear PME SCI status and disable SCI, then PCIEXP_WAKE_STS from PMC.
|
|
This prevents platform from waking more than one time due to a single PCIE wake event.
|
|
Normally it's up to OS to clear SCI statuses. But in a scenario where platform wakes
|
|
and goes to S5 instead of booting to OS, the SCI status would remain set and would trigger another wake.
|
|
**/
|
|
VOID
|
|
ClearPcieSci (
|
|
VOID
|
|
);
|
|
|
|
|
|
/**
|
|
Performs update of SmiDispatch descriptors with values that have to be evaluated during runtime.
|
|
**/
|
|
VOID
|
|
PchSmiDispatchUpdateDescriptors (
|
|
VOID
|
|
);
|
|
|
|
#endif
|