313 lines
8.6 KiB
C
313 lines
8.6 KiB
C
/** @file
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Header file for the SA Init PEIM
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _SA_INIT_LIB_H_
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#define _SA_INIT_LIB_H_
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#include <Ppi/SiPolicy.h>
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#include <SaDataHob.h>
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#include <SaConfigHob.h>
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#include <CpuPcieHobGen3.h>
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#include <CpuPcieHob.h>
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#include <Library/PcdLib.h>
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#include <Base.h>
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#include <Library/PeiGraphicsInitLib.h>
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#include <Library/PcdLib.h>
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#define MAX_ADDRESS_32BIT 0xFFFFFFFF
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typedef struct {
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UINT32 BaseAddr;
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UINT32 Offset;
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UINT32 AndMask;
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UINT32 OrMask;
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} BOOT_SCRIPT_REGISTER_SETTING;
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//
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// Functions
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//
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/**
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Check some SA policies are valid for debugging unexpected problem if these
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values are not initialized or assigned incorrect resource.
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@param[in] SiPreMemPolicyPpi The SI PreMem Policy instance
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**/
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VOID
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SaValidatePolicy (
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IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
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);
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/**
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<b>System Agent Initialization for early PEIM phase</b> \n
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- <b>Introduction</b> \n
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This module incorporates all SA initialization code required in PEI phase (early POST). Programming all needed System Agent BARs, initializing DMI link Gen2 (or Gen1), initializing PciExpress (PEG controller bifurcation) and Graphics (iGfx or external), and initializing DMI TC/VC mapping. This module needs to get executed before MRC.
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- @pre
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- SI_POLICY_PPI
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- _SI_CPU_POLICY_PPI
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- _PEI_STALL_PPI
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- @result
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All required SA BARs in PEI phase are initialized in this module (e.g. MCH_BAR, DMI_BAR and EP_BAR) with the data from SI_POLICY_PPI. PciExpress controllers (PEG Ports) are initialized based on the PEG bifurcation strapping and slot population; iGfx is initialized if no other external graphics is present; Via PCH_INIT_PPI, DMI GenX is programmed, TC/VC mapping is programmed and all SA and PCH VCs are polled for negotiation completion.
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- SA_DATA_HOB: A HOB created, containing a GUID and the some information about PEG and SMI.
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@retval EFI_SUCCESS Function executed successfully
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@retval EFI_NOT_FOUND The required PPI could not be located.
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**/
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EFI_STATUS
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EFIAPI
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SaOnPolicyInstalled (
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VOID
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);
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/**
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SA late PEI Initialization.
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@retval EFI_SUCCESS Function executed successfully
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@retval EFI_NOT_FOUND The required PPI could not be located.
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**/
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EFI_STATUS
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EFIAPI
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SaInit (
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VOID
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);
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/**
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Programs Sa Bars
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@param[in] MiscPeiPreMemConfig - Instance of SA_MISC_PEI_PREMEM_CONFIG
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**/
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VOID
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ProgramSaBars (
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IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig
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);
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/**
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Init and Install SA Hob
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@param[in] MiscPeiPreMemConfig - Instance of SA_MISC_PEI_PREMEM_CONFIG
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@param[out] SaDataHob - SA_DATA_HOB instance installed by this function
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@param[out] SaConfigHob - SA_CONFIG_HOB instance installed by this function
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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InstallSaHob (
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IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig,
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OUT SA_DATA_HOB **SaDataHobOut,
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OUT SA_CONFIG_HOB **SaConfigHobOut
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);
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/**
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Report the SA PCIe initialization code version.
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@param[in] HostBridgePreMemConfig - Instance of SA_MISC_PEI_PREMEM_CONFIG
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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ReportPcieVersion (
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IN HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig
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);
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/**
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Create and Init Graphics Data Hob
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@param[in] MiscPeiPreMemConfig - Instance of SA_MISC_PEI_PREMEM_CONFIG
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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CreateGfxDataHob (
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IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig
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);
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/**
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BIOS_CPL_BIT is set for processor to activate the power and thermal management
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features on the platform.
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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SaResetComplete (
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VOID
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);
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/**
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Function to handle SA at end of PEI
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@retval None
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**/
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EFI_STATUS
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EFIAPI
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SaOnEndOfPei (
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VOID
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);
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/**
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This function handles SA S3 resume task
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@retval EFI_STATUS - Always return EFI_SUCCESS
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**/
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EFI_STATUS
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SaS3ResumeAtEndOfPei (
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VOID
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);
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/**
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This function enumerate all downstream bridge.
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@param[in] BusNum - Primary bus number of current bridge
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@retval Current bus number: if current bus is an enpoint device
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@retval subordinate bus number: if current bus is a bridge
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**/
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UINT8
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EnumerateDownstream (
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IN UINT8 BusNum
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);
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/**
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Find the MMIO size that a given PCI device requires
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@param[in] BusNum - Bus number of the device
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@param[in] DevNum - device Number of the device
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@param[in] FunNum - Function number of the device
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@param[out] MmioLength - MMIO Length in bytes
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**/
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VOID
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FindPciDeviceMmioLength (
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IN UINT32 BusNum,
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IN UINT32 DevNum,
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IN UINT32 FunNum,
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OUT UINT32 *MmioLength
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);
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/**
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Check if device has a legacy only OpROM (CSM required to dispatch device's OpROM)
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@param[in] OpRomScanTempMmioBar - Temporary BAR to MMIO map OpROMs during VGA scanning
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@param[in] OpRomScanTempMmioLimit - Limit address for OpROM MMIO range
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@param[in] EpSegment - Segment number for end point to check
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@param[in] EpBus - Bus number for end point to check
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@param[in] EpDev - Device number for end point to check
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@param[in] EpFunc - Function number for end point to check
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@retval TRUE if end point has a legacy only OpROM
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@retval FALSE if end point has a UEFI OpROM, Hybrid OpROM, or no OpROM
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**/
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BOOLEAN
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CheckForLegacyOnlyOpRom (
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IN UINT32 OpRomScanTempMmioBar,
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IN UINT32 OpRomScanTempMmioLimit,
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IN UINT8 EpSegment,
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IN UINT8 EpBus,
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IN UINT8 EpDev,
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IN UINT8 EpFunc
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);
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/**
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Disable IGD VGA Decode Bits
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**/
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VOID
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DisableIgdVgaDecodeBits (
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VOID
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);
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/**
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Enable VLW's
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@param[in] HostBridgePreMemConfig Instance of HOST_BRIDGE_PREMEM_CONFIG
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**/
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VOID
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VlwEnable (
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IN HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig
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);
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/**
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CheckOffboardPcieVga: Check if off board PCIe graphics Card is present
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@param[in, out] PchPcieMmioLength - Total PCIe MMIO length on all PCH root ports
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@param[in, out] PrimaryDisplay - Primary Display - default is IGD
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@param[in] OpRomScanTempMmioBar - Temporary BAR to MMIO map OpROMs during VGA scanning
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@param[in] OpRomScanTempMmioLimit - Limit address for OpROM MMIO range
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@param[in] ScanForLegacyOpRom - TRUE to scan for legacy only VBIOS, FALSE otherwise
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@param[out] FoundLegacyOpRom - If legacy only VBIOS found, returns TRUE
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@param[in] ResizableBarSupport - Resizable BAR is support
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**/
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VOID
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CheckOffboardPcieVga (
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IN OUT UINT32 *PchPcieMmioLength,
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IN OUT DISPLAY_DEVICE *PrimaryDisplay,
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IN UINT32 OpRomScanTempMmioBar,
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IN UINT32 OpRomScanTempMmioLimit,
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IN BOOLEAN ScanForLegacyOpRom,
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OUT BOOLEAN *FoundLegacyOpRom,
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IN UINT8 ResizableBarSupport
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);
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/**
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Print SA PCI space in Debug log.
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@retval None
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**/
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VOID
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SaPciPrint (
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VOID
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);
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/**
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Set SAPMCTL Register.
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@retval None
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**/
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VOID
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SetSaPmCtlReg (
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VOID
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);
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/**
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This function is to Set BIOS_RESET_CPL bits
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@retval None
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**/
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VOID
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SetBiosResetCpl (
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VOID
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);
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#endif
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