645 lines
22 KiB
C
645 lines
22 KiB
C
/** @file
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This is the driver that initializes the Intel System Agent.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2014 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "SaInitDxe.h"
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#include "SaInit.h"
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#include <SaConfigHob.h>
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#include <Protocol/SaNvsArea.h>
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#include <Library/PchInfoLib.h>
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#include <Library/DxeIpuInit.h>
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#include <Library/DxeTraceHubInit.h>
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#if FixedPcdGetBool(PcdITbtEnable) == 1
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#include <Library/DxeTcssInit.h>
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#include <Register/CpuUsbRegs.h>
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#endif
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#include <Library/PreSiliconEnvDetectLib.h>
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#include <Register/TraceHubRegs.h>
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#include <CpuPcieInfo.h>
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#include <Library/AslUpdateLib.h>
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#include <Library/DxeHybridGraphicsInitLib.h>
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#include <Library/DxeCpuPcieRpLib.h>
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#include <SaConfigHob.h>
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#include <CpuPcieHob.h>
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#include <HostBridgeDataHob.h>
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#if (FixedPcdGetBool (PcdVmdEnable) == 1)
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#include <Library/VmdInfoLib.h>
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#include <Register/VmdRegs.h>
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#include <VmdInfoHob.h>
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#include <Library/SataSocLib.h>
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#include <PchBdfAssignment.h>
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#endif
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#include <Library/CpuPlatformLib.h>
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#include <Library/DxeSaInitFruLib.h>
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#include <Library/PeiDxeSmmReserveMmio64SizeLib.h>
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#include <Register/Cpuid.h>
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///
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/// Global Variables
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///
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GLOBAL_REMOVE_IF_UNREFERENCED SYSTEM_AGENT_NVS_AREA_PROTOCOL mSaNvsAreaProtocol;
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GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy;
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/**
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A protocol callback which updates 64bits MMIO Base and Length in SA GNVS area
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**/
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VOID
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UpdateSaGnvsForMmioResourceBaseLength (
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VOID
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)
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{
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EFI_PHYSICAL_ADDRESS PciBaseAddress;
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UINT32 Tolud;
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UINT64 Length;
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UINT64 McD0BaseAddress;
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UINTN ResMemLimit1;
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BOOLEAN EnableAbove4GBMmioBiosAssignemnt;
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VOID *CpuHob;
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UINT8 PhysicalAddressBits;
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UINT64 PhysicalAddressLimit;
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PciBaseAddress = 0;
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Tolud = 0;
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Length = 0;
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ResMemLimit1 = 0;
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EnableAbove4GBMmioBiosAssignemnt = CheckAbove4GbMmio ();
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CpuHob = NULL;
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PhysicalAddressBits = 0;
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PhysicalAddressLimit = 0;
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//
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// Read memory map registers
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//
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McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, 0);
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Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
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PciBaseAddress = Tolud;
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ResMemLimit1 = (UINTN) PcdGet64 (PcdSiPciExpressBaseAddress);
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Length = ResMemLimit1 - PciBaseAddress;
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CpuHob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (CpuHob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) CpuHob)->SizeOfMemorySpace;
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PhysicalAddressLimit = LShiftU64 (1, PhysicalAddressBits);
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}
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//
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// Check Enable Above 4GB MMIO or not
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//
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DEBUG ((DEBUG_INFO, "Update SA GNVS Area.\n"));
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mSaNvsAreaProtocol.Area->Mmio32Base = (UINT32) PciBaseAddress;
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mSaNvsAreaProtocol.Area->Mmio32Length = (UINT32) Length;
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if (EnableAbove4GBMmioBiosAssignemnt == TRUE) {
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if (PhysicalAddressBits != 0 && ( PhysicalAddressLimit % 0x4000000000) == 0) { // Checking Memory Size multiples of 256GB
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mSaNvsAreaProtocol.Area->Mmio64Base = BASE_256GB;
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//
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// Some platforms need to reserve MMIO space from PhysicalAddressLimit for P2SB usage.
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//
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mSaNvsAreaProtocol.Area->Mmio64Length = PhysicalAddressLimit - mSaNvsAreaProtocol.Area->Mmio64Base - ReserveMmio64Size ();
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} else {
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mSaNvsAreaProtocol.Area->Mmio64Base = BASE_256GB;
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mSaNvsAreaProtocol.Area->Mmio64Length = SIZE_256GB;
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}
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}
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio64Base = %lx\n", mSaNvsAreaProtocol.Area->Mmio64Base));
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio64Length = %lx\n", mSaNvsAreaProtocol.Area->Mmio64Length));
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio32Base = %lx\n", mSaNvsAreaProtocol.Area->Mmio32Base));
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio32Length = %lx\n", mSaNvsAreaProtocol.Area->Mmio32Length));
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}
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/**
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Initialize SA Nvs Area operation region.
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@retval EFI_SUCCESS initialized successfully
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@retval EFI_NOT_FOUND Nvs Area operation region is not found
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**/
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EFI_STATUS
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PatchSaNvsAreaAddress (
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VOID
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)
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{
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EFI_STATUS Status;
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UINT32 Address;
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UINT16 Length;
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Address = (UINT32) (UINTN) mSaNvsAreaProtocol.Area;
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Length = (UINT16) sizeof (SYSTEM_AGENT_NVS_AREA);
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DEBUG ((DEBUG_INFO, "PatchSaNvsAreaAddress: SA NVS Address %x Length %x\n", Address, Length));
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Status = UpdateNameAslCode (SIGNATURE_32 ('S','A','N','B'), &Address, sizeof (Address));
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ASSERT_EFI_ERROR (Status);
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Status = UpdateNameAslCode (SIGNATURE_32 ('S','A','N','L'), &Length, sizeof (Length));
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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/**
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Install SSDT Table
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@retval EFI_SUCCESS - SSDT Table load successful.
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**/
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EFI_STATUS
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InstallSsdtAcpiTable (
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IN GUID SsdtTableGuid,
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IN UINT64 Signature
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)
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{
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EFI_STATUS Status;
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EFI_HANDLE *HandleBuffer;
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BOOLEAN LoadTable;
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UINTN NumberOfHandles;
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UINTN Index;
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INTN Instance;
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UINTN Size;
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UINT32 FvStatus;
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UINTN TableHandle;
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EFI_FV_FILETYPE FileType;
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EFI_FV_FILE_ATTRIBUTES Attributes;
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EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
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EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
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EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
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EFI_ACPI_COMMON_HEADER *Table;
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FwVol = NULL;
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Table = NULL;
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DEBUG ((DEBUG_INFO, "Loading SSDT Table GUID: %g\n", SsdtTableGuid));
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///
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/// Locate FV protocol.
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///
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Status = gBS->LocateHandleBuffer (
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ByProtocol,
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&gEfiFirmwareVolume2ProtocolGuid,
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NULL,
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&NumberOfHandles,
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&HandleBuffer
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// Look for FV with ACPI storage file
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///
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for (Index = 0; Index < NumberOfHandles; Index++) {
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///
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/// Get the protocol on this handle
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/// This should not fail because of LocateHandleBuffer
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///
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Status = gBS->HandleProtocol (
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HandleBuffer[Index],
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&gEfiFirmwareVolume2ProtocolGuid,
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(VOID **) &FwVol
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);
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ASSERT_EFI_ERROR (Status);
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if (FwVol == NULL) {
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return EFI_NOT_FOUND;
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}
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///
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/// See if it has the ACPI storage file
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///
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Size = 0;
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FvStatus = 0;
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Status = FwVol->ReadFile (
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FwVol,
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&SsdtTableGuid,
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NULL,
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&Size,
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&FileType,
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&Attributes,
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&FvStatus
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);
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///
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/// If we found it, then we are done
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///
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if (!EFI_ERROR (Status)) {
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break;
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}
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}
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///
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/// Our exit status is determined by the success of the previous operations
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/// If the protocol was found, Instance already points to it.
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///
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///
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/// Free any allocated buffers
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///
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FreePool (HandleBuffer);
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///
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/// Sanity check that we found our data file
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///
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ASSERT (FwVol);
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///
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/// Locate ACPI tables
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///
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Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
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///
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/// Read tables from the storage file.
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///
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if (FwVol == NULL) {
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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return EFI_NOT_FOUND;
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}
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Instance = 0;
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while (Status == EFI_SUCCESS) {
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///
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/// Read the ACPI tables
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///
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Status = FwVol->ReadSection (
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FwVol,
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&SsdtTableGuid,
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EFI_SECTION_RAW,
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Instance,
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(VOID **) &Table,
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&Size,
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&FvStatus
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);
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if (!EFI_ERROR (Status)) {
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///
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/// check and load HybridGraphics SSDT table
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///
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LoadTable = FALSE;
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TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
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if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId == Signature) {
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///
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/// This is the SSDT table that match the Signature
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///
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DEBUG ((DEBUG_INFO, "Found out SSDT Table GUID: %g\n", SsdtTableGuid));
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LoadTable = TRUE;
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}
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///
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/// Add the table
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///
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if (LoadTable) {
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TableHandle = 0;
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Status = AcpiTable->InstallAcpiTable (
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AcpiTable,
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TableHeader,
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TableHeader->Length,
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&TableHandle
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);
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}
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///
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/// Increment the instance
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///
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Instance++;
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Table = NULL;
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}
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}
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return EFI_SUCCESS;
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}
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/**
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This function gets registered as a callback to perform Dmar Igd
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@param[in] Event - A pointer to the Event that triggered the callback.
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@param[in] Context - A pointer to private data registered with the callback function.
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**/
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VOID
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EFIAPI
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SaAcpiEndOfDxeCallback (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "%a - Start\n", __FUNCTION__));
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, PCI_VENDOR_ID_OFFSET)) != 0xFFFF) {
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Status = PostPmInitEndOfDxe ();
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if (EFI_SUCCESS != Status) {
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DEBUG ((DEBUG_WARN, "[SA] EndOfDxe GraphicsInit Error, Status = %r \n", Status));
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ASSERT_EFI_ERROR (Status);
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}
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}
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, PCI_VENDOR_ID_OFFSET)) != 0xFFFF) {
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Status = GetVbtEndOfDxe ();
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if (EFI_SUCCESS != Status) {
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DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Op Region Error, Status = %r \n", Status));
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}
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Status = UpdateIgdOpRegionEndOfDxe ();
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if (EFI_SUCCESS != Status) {
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DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Update Op Region Error, Status = %r \n", Status));
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}
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}
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PatchSaNvsAreaAddress();
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DEBUG ((DEBUG_INFO, "%a - End\n", __FUNCTION__));
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return;
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}
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#if (FixedPcdGetBool (PcdVmdEnable) == 1)
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/**
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Initializes VMD NVS area.
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**/
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VOID
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VmdNvsInit (
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VOID
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)
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{
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VMD_INFO_HOB *VmdInfoHob;
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UINT8 VmdDevIndex;
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CPU_GENERATION CpuGeneration;
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CPU_FAMILY CpuFamily;
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VmdInfoHob = NULL;
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VmdInfoHob = (VMD_INFO_HOB *) GetFirstGuidHob (&gVmdInfoHobGuid);
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if (VmdInfoHob == NULL) {
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DEBUG ((DEBUG_INFO, "Vmd Info Hob not found\n"));
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return;
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}
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if ((mSaNvsAreaProtocol.Area->VmdEnable = IsVmdEnabled ()) == 1) {
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mSaNvsAreaProtocol.Area->VmdSataPort0to7 = 0;
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mSaNvsAreaProtocol.Area->VmdCpuRp = 0;
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mSaNvsAreaProtocol.Area->VmdRp1to8 = 0;
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mSaNvsAreaProtocol.Area->VmdRp9to16 = 0;
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mSaNvsAreaProtocol.Area->VmdRp17to24 = 0;
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CpuGeneration = GetCpuGeneration ();
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CpuFamily = GetCpuFamily ();
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if (VmdInfoHob != NULL) {
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for (VmdDevIndex = 0; VmdDevIndex < VMD_MAX_DEVICES; ++VmdDevIndex) {
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if (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].PortEn) {
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if (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == SataDevNumber (0)) {
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DEBUG ((DEBUG_INFO, "SA VMD NVS protocol - SATA is mapped under VMD\n"));
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mSaNvsAreaProtocol.Area->VmdSataPort0to7 |= 0xFF;
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}
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if (CpuGeneration == EnumAdlCpu
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) {
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if (CpuFamily == CPUID_FULL_FAMILY_MODEL_ALDERLAKE_DT_HALO
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) {
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if ((VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == SA_PEG1_DEV_NUM) && (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc == SA_PEG1_FUN_NUM)) {
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DEBUG ((DEBUG_INFO, "SA VMD NVS protocol - PEG11 Port - BDF 0/1/1 is mapped under VMD\n"));
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mSaNvsAreaProtocol.Area->VmdCpuRp |= 0x2;
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}
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} else if (CpuFamily == CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE
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) {
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if ((VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == SA_PEG3_DEV_NUM) && (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc == SA_PEG2_FUN_NUM)) {
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DEBUG ((DEBUG_INFO, "SA VMD NVS protocol - PEG62 Port - BDF 0/6/2 is mapped under VMD\n"));
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mSaNvsAreaProtocol.Area->VmdCpuRp |= 0x10;
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}
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}
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}
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if ((VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == SA_PEG0_DEV_NUM) && (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc == SA_PEG0_FUN_NUM)) {
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DEBUG ((DEBUG_INFO, "SA VMD NVS protocol - PEG10 Port - BDF 0/1/0 is mapped under VMD\n"));
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mSaNvsAreaProtocol.Area->VmdCpuRp |= 0x1;
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} else if ((VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == SA_PEG2_DEV_NUM) && (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc == SA_PEG2_FUN_NUM)) {
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DEBUG ((DEBUG_INFO, "SA VMD NVS protocol - PEG12 Port - BDF 0/1/2 is mapped under VMD\n"));
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mSaNvsAreaProtocol.Area->VmdCpuRp |= 0x4;
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} else if ((VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == SA_PEG3_DEV_NUM) && (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc == SA_PEG3_FUN_NUM)){
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DEBUG ((DEBUG_INFO, "SA VMD NVS protocol - PEG60 Port - BDF 0/6/0 is mapped under VMD\n"));
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mSaNvsAreaProtocol.Area->VmdCpuRp |= 0x8;
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} else {
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DEBUG ((DEBUG_INFO, "SA VMD NVS protocol - PCH PCIe is remapped under VMD\n"));
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if (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1) {
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mSaNvsAreaProtocol.Area->VmdRp1to8 |= 0x1 << (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc);
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} else if (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9) {
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mSaNvsAreaProtocol.Area->VmdRp9to16 |= 0x1 << (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc);
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} else if (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17) {
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mSaNvsAreaProtocol.Area->VmdRp17to24 |= 0x1 << (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc);
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} else if (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpDev == PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25) {
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mSaNvsAreaProtocol.Area->VmdRp25to32 |= 0x1 << (VmdInfoHob->VmdPortInfo.PortInfo[VmdDevIndex].RpFunc);
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}
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}
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}
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}
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}
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}
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}
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#endif
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/**
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SystemAgent Acpi Initialization.
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@param[in] ImageHandle Handle for the image of this driver
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_OUT_OF_RESOURCES No enough buffer to allocate
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**/
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EFI_STATUS
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EFIAPI
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SaAcpiInit (
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IN EFI_HANDLE ImageHandle
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)
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{
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EFI_STATUS Status;
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CPUID_VERSION_INFO_EAX CpuidVersionInfoEax;
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EFI_EVENT EndOfDxeEvent;
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PCIE_DXE_CONFIG *PcieDxeConfig;
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#if FixedPcdGetBool (PcdITbtEnable) == 1
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TCSS_DATA_HOB *TcssHob;
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BOOLEAN CpuXhciExisted;
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#endif
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CPU_PCIE_HOB *CpuPcieHob;
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#if FixedPcdGetBool (PcdITbtEnable) == 1
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CpuXhciExisted = FALSE;
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#endif
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AsmCpuid (CPUID_VERSION_INFO, &CpuidVersionInfoEax.Uint32, NULL, NULL, NULL);
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///
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/// Get the platform setup policy.
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///
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Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) &mSaPolicy);
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ASSERT_EFI_ERROR (Status);
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///
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/// Install System Agent Global NVS protocol
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///
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DEBUG ((DEBUG_INFO, "Install SA GNVS protocol\n"));
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Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (SYSTEM_AGENT_NVS_AREA), (VOID **) &mSaNvsAreaProtocol.Area);
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ASSERT_EFI_ERROR (Status);
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ZeroMem ((VOID *) mSaNvsAreaProtocol.Area, sizeof (SYSTEM_AGENT_NVS_AREA));
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mSaNvsAreaProtocol.Area->XPcieCfgBaseAddress = (UINT32) (PcdGet64 (PcdSiPciExpressBaseAddress));
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mSaNvsAreaProtocol.Area->CpuIdInfo = CpuidVersionInfoEax.Uint32;
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#if (FixedPcdGetBool (PcdVmdEnable) == 1)
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VmdNvsInit ();
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#endif
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///
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/// Get CpuPcieHob HOB
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///
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CpuPcieHob = NULL;
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CpuPcieHob = (CPU_PCIE_HOB *) GetFirstGuidHob (&gCpuPcieHobGuid);
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if (CpuPcieHob == NULL) {
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DEBUG((DEBUG_ERROR, "CpuPcieHob not found\n"));
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// @todo: Will add it back once it will get add into NVS library since currently it is failing for JSL
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//ASSERT(CpuPcieHob != NULL);
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//return EFI_NOT_FOUND;
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} else {
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mSaNvsAreaProtocol.Area->SlotSelection = CpuPcieHob->SlotSelection;
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DEBUG((DEBUG_INFO, "RpEnabledMask == %x\n", CpuPcieHob->RpEnabledMask));
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if (CpuPcieHob->RpEnabledMask == 0) {
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DEBUG ((DEBUG_ERROR, "All CPU PCIe root ports are disabled!!\n"));
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} else {
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if (CpuPcieHob->RpEnabledMask & BIT0) {
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mSaNvsAreaProtocol.Area->CpuPcieRp0Enable = 1;
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}
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if (CpuPcieHob->RpEnabledMask & BIT1) {
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mSaNvsAreaProtocol.Area->CpuPcieRp1Enable = 1;
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}
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if (CpuPcieHob->RpEnabledMask & BIT2) {
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mSaNvsAreaProtocol.Area->CpuPcieRp2Enable = 1;
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}
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if (CpuPcieHob->RpEnabledMask & BIT3) {
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mSaNvsAreaProtocol.Area->CpuPcieRp3Enable = 1;
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}
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}
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mSaNvsAreaProtocol.Area->MaxPegPortNumber = GetMaxCpuPciePortNum ();
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Status = GetConfigBlock ((VOID *)mSaPolicy, &gPcieDxeConfigGuid, (VOID *)&PcieDxeConfig);
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ASSERT_EFI_ERROR (Status);
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}
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mSaNvsAreaProtocol.Area->SimicsEnvironment = (UINT8) IsSimicsEnvironment ();
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Status = gBS->InstallMultipleProtocolInterfaces (
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&ImageHandle,
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&gSaNvsAreaProtocolGuid,
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&mSaNvsAreaProtocol,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// GtPostInit Initialization
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///
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DEBUG ((DEBUG_INFO, "Initializing GT ACPI tables\n"));
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GraphicsInit (ImageHandle, mSaPolicy);
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///
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/// Audio (dHDA) Initialization
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///
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///
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/// Vtd Initialization
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///
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DEBUG ((DEBUG_INFO, "Initializing VT-d ACPI tables\n"));
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VtdInit (mSaPolicy);
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///
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/// IgdOpRegion Install Initialization
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///
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DEBUG ((DEBUG_INFO, "Initializing IGD OpRegion\n"));
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IgdOpRegionInit ();
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///
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/// Register an end of DXE event for SA ACPI to do tasks before invoking any UEFI drivers,
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/// applications, or connecting consoles,...
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///
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_CALLBACK,
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SaAcpiEndOfDxeCallback,
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NULL,
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&gEfiEndOfDxeEventGroupGuid,
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&EndOfDxeEvent
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);
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///
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/// Install System Agent Global NVS ACPI table
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///
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Status = InstallSsdtAcpiTable (gSaSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'a', 'S', 's', 'd', 't', ' ', 0));
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ASSERT_EFI_ERROR (Status);
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///
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/// Update CPU PCIE RP NVS AREA
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///
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UpdateCpuPcieNVS();
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///
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/// Install Intel Graphics SSDT
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///
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Status = InstallSsdtAcpiTable (gGraphicsAcpiTableStorageGuid, SIGNATURE_64 ('I','g','f','x','S','s','d','t'));
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ASSERT_EFI_ERROR (Status);
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#if FixedPcdGetBool(PcdITbtEnable) == 1
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if (0xFFFF != PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (0, XHCI_NORTH_BUS_NUM, XHCI_NORTH_DEV_NUM, XHCI_NORTH_FUNC_NUM, PCI_VENDOR_ID_OFFSET))) {
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CpuXhciExisted = TRUE;
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}
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if (CpuXhciExisted == TRUE) {
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///
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/// Get TcssHob HOB
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///
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TcssHob = (TCSS_DATA_HOB *) GetFirstGuidHob (&gTcssHobGuid);
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///
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/// Install SEG SSDT table only if Multiple Segment is enabled
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///
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if (TcssHob != NULL) {
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if (TcssHob->TcssData.PcieMultipleSegmentEnabled) {
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Status = InstallSsdtAcpiTable (gSegSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S','e','g','S','s','d','t',0));
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ASSERT_EFI_ERROR (Status);
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}
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///
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/// Install TCSS SSDT Table
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///
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Status = InstallSsdtAcpiTable (gTcssSsdtAcpiTableStorageGuid, SIGNATURE_64 ('T','c','s','s','S','s','d','t'));
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ASSERT_EFI_ERROR (Status);
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///
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/// Update TCSS NVS AREA tables
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///
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UpdateTcssNVS();
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}
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}
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#endif
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///
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/// Install IPU SSDT if IPU is present.
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///
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IPU_BUS_NUM, IPU_DEV_NUM, IPU_FUN_NUM, 0)) != V_SA_DEVICE_ID_INVALID) {
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Status = InstallSsdtAcpiTable (gIpuAcpiTableStorageGuid, SIGNATURE_64 ('I','p','u','S','s','d','t',0));
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ASSERT_EFI_ERROR (Status);
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///
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/// Update IPU NVS AREA tables
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///
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UpdateIpuNvs();
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}
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DEBUG ((DEBUG_INFO, "Initializing Hybrid Graphics (Dxe)\n"));
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#if FixedPcdGetBool(PcdHgEnable) == 1
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DxeHybridGraphicsInit();
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#endif
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return EFI_SUCCESS;
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}
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