241 lines
7.2 KiB
Plaintext
241 lines
7.2 KiB
Plaintext
/** @file
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This file describes the contents of the ACPI DMA address Remapping
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Intel Peripheral Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include "Dmar.h"
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#include <Register/P2sbRegs.h>
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EFI_ACPI_DMAR_TABLE DmarTable = {
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//
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// EFI_ACPI_DMAR_HEADER
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//
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{
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//
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// EFI_ACPI_DESCRIPTION_HEADER
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//
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{
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EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE,
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sizeof (EFI_ACPI_DMAR_TABLE),
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EFI_ACPI_DMAR_TABLE_REVISION,
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//
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// Checksum will be updated at runtime
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//
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0x00,
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//
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// It is expected that these values will be programmed at runtime
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//
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{ 'I', 'N', 'T', 'E', 'L', ' ' },
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EFI_ACPI_DMAR_OEM_TABLE_ID,
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0x1,
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EFI_ACPI_DMAR_OEM_CREATOR_ID,
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1
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},
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//
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// DMAR table specific entries below:
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//
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//
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// 39-bit addressing Host Address Width
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//
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38,
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//
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// Flags
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//
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0,
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//
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// Reserved fields
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//
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
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},
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//
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// First DRHD structure, VT-d Engine #1
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//
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{
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//
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// EFI_ACPI_DMAR_DRHD_HEADER
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//
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{
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{0, // Type = 0 (DRHD)
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sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT)}, // Length of structure
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0, // Flag - Do not include all
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0, // Reserved fields
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0, // Segment
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0 // Base address of DMA-remapping hardware - Updated at boot time
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},
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//
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// Device Scopes
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//
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{
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{
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{1, // Type
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sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
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0, // Segment number
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0, // Reserved
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0}, // Start bus number
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{2, 0} // PCI path
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}
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}
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},
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#if FixedPcdGetBool(PcdIpuEnable) == 1
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//
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// Second DRHD structure, VT-d Engine #2
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//
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{
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//
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// EFI_ACPI_DMAR_DRHD_HEADER
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//
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{
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{0, // Type = 0 (DRHD)
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sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT)}, // Length of structure
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0, // Flag - Do not include all
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0, // Reserved fields
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0, // Segment
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0 // Base address of DMA-remapping hardware - Updated at boot time
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},
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//
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// Device Scopes
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//
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{
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{
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{1, // Type
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sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
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0, // Segment number
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0, // Reserved
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0}, // Start bus number
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{5, 0} // PCI path
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}
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}
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},
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#endif
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//
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//Third DRHD structure VT-d Engine# 3
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//
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{
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//
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// EFI_ACPI_DMAR_DRHD_HEADER
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//
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{
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{0, // Type = 0 (DRHD)
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sizeof (EFI_ACPI_DRHD_ENGINE3_STRUCT)}, // Length of strucure.
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1, // Flag - Include all
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0, // Reserved
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0, // Segment Number
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0 // Base address of DMA-remapping hardware.
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},
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{
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//
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// Device Scopes
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//
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{
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{3, // Type=IO APIC
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sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
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0, // Reserved
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2, // Enumeration ID
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V_P2SB_CFG_IBDF_BUS}, // Start bus number
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{V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC} // PCI path
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},
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//
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// Device Scopes
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//
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{
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{4, // Type=HPET
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sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
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0, // Reserved
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0, // Enumeration ID
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V_P2SB_CFG_HBDF_BUS}, // Start bus number
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{V_P2SB_CFG_HBDF_DEV, V_P2SB_CFG_HBDF_FUNC} // PCI path
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}
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}
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},
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//RMRR structure for IGD device.
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{
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//
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// EFI_ACPI_DMAR_RMRR_HEADER
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//
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{
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{
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0x1, // Type 1 - RMRR structure
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sizeof(EFI_ACPI_RMRR_IGD_STRUC) // Length
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},
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{ 0x00, 0x00 }, // Reserved
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0x0000, // Segment Num
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0x0000000000000000, // RMRR Base address - Updated in runtime.
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0x0000000000000000 // RMRR Limit address - Updated in runtime.
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},
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//
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// Device Scopes
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//
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{
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{
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{1, // Type
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sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
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0, // Reserved
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0, // Enum ID
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0}, // Start bus number
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{2, 0} // PCI path
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}
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}
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}
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};
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//
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// Dummy function required for build tools
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//
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#if defined (__GNUC__)
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VOID*
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ReferenceAcpiTable (
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VOID
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)
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{
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//
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// Reference the table being generated to prevent the optimizer from removing the
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// data structure from the exeutable
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//
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return (VOID*)&DmarTable;
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}
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#else
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int
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main (
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VOID
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)
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{
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return 0;
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}
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#endif
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